Backside-Fed ESD Clamp Layout With Shared Diode Tap Regions
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Solution Overview
Problem
The miniaturization of integrated circuits has increased their susceptibility to electrostatic discharge (ESD) events, leading to potential electronic circuit damage due to thinner dielectric thicknesses and lowered dielectric breakdown voltages.
Innovation Solution
An ESD protection circuit is implemented using a first and second diode, coupled between an input/output pad and a reference voltage supply, and an ESD clamp circuit, which shares signal tap regions with these diodes, reducing area and resistance, and includes a conductive structure on the semiconductor wafer to provide a reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional ESD protection circuits are used, then ESD protection is provided, but the circuit occupies more area and has higher resistance
Solution Approach 1:
The ESD clamp circuit shares signal tap regions with the first and second diodes, merging previously separate structures into a unified design. This reduces the total area occupied by the ESD protection circuit while maintaining full ESD protection functionality through shared conductive paths and tap regions.
Solution Approach 2:
The signal tap regions serve multiple functions: they provide reference voltages for the ESD clamp circuit and simultaneously serve as connection points for the diodes. This multi-functionality reduces the number of separate components needed, thereby reducing overall circuit area and resistance.
2Reliability
If traditional ESD protection circuits are used, then ESD protection is provided, but the circuit has higher resistance and slower operation
Solution Approach 1:
By merging the ESD clamp circuit with the diode structures through shared signal tap regions, the patent creates shorter current paths with fewer discrete connections. This reduces overall resistance and enables faster ESD discharge operation while maintaining protection capability.
3Volume of moving object
If miniaturization is pursued, then device size is reduced and power consumption is lowered, but susceptibility to ESD events increases
Solution Approach 1:
The patent integrates ESD protection functionality directly into the miniaturized device structure by sharing signal tap regions between the diodes and ESD clamp circuit. This merged design provides robust ESD protection within a compact footprint, addressing ESD susceptibility without increasing device size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD protection circuit effectively discharges ESD events with lower clamping voltage and faster operation, occupying less area and having less resistance than traditional approaches.
Implementation Method 1
The first diode is coupled to and configured to conduct an electrostatic discharge (ESD) current from the IO pad to the first signal tap of the ESD clamp circuit. The second diode is coupled to and configured to conduct an ESD current from the IO pad to the second signal tap of the ESD clamp circuit.
Implementation Method 2
The ESD clamp circuit is in the semiconductor wafer, and is coupled to the first diode and the second diode. The first signal tap region is coupled to a first voltage supply. The second signal tap region is coupled to a second voltage supply different from the first voltage supply.
Data Source
AI summary
An electrostatic discharge (ESD) protection circuit includes a first and second diode in a semiconductor wafer, an ESD clamp circuit and a first conductive structure on a backside of a semiconductor wafer. The first diode is coupled between an input output (IO) pad and a first node. The second diode is coupled to the first diode, and coupled between the IO pad and a second node. The ESD clamp circuit is in the semiconductor wafer, coupled to the first and second node, and between the first and second diode. The ESD clamp circuit includes a first signal tap region in the semiconductor wafer that is coupled to a reference voltage supply. The second diode is coupled to and configured to share the first signal tap region with the ESD clamp circuit. The first conductive structure is configured to provide a reference voltage to the first signal tap region.