Backside Contact Structures with FEOL Silicide Formation

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Solution Overview

Problem

Existing semiconductor devices face limitations in forming high-quality silicide layers on backside contact structures due to the constraints of forming such layers in the BEOL process, which restricts the annealing temperature below the melting point of BEOL structures, thereby limiting the quality of the silicide layer and the performance of backside contact connections.

Innovation Solution

The formation of silicide layers is performed in the FEOL process at temperatures of 900 °C or above, allowing for higher-quality silicide layers to be formed before the BEOL process, thereby improving the connection performance of backside contact structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If silicide layer is formed in BEOL process, then BEOL structure integrity is maintained, but silicide layer quality is limited due to temperature constraints

Engineering Contradiction:
Improvesilicide layer qualityVSAvoidannealing temperature
Core Design Contradiction:
Manufacturing precisionVSTemperature

Solution Approach 1:

The silicide layer is formed in the FEOL process before the BEOL process begins. This preliminary action allows the silicide layer to be formed at high temperatures (900°C or above) without risking damage to BEOL structures, as the BEOL structures do not yet exist. The placeholder structure is prepared in advance to receive the high-temperature silicide formation process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The manufacturing process is segmented into distinct phases: FEOL process for forming the silicide layer at high temperatures, followed by BEOL process for forming interconnect structures. This segmentation allows each process to operate at optimal conditions without interfering with the other, resolving the temperature-quality contradiction.

Inventive Principle:
Principle #1Segmentation

2Reliability

If annealing temperature is increased to improve silicide layer quality, then connection performance improves, but risk of melting BEOL structures increases

Engineering Contradiction:
Improveconnection performanceVSAvoidrisk of melting BEOL structures
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The silicide layer is formed in the FEOL process before the BEOL process begins. This preliminary action allows the silicide layer to be formed at high temperatures (900°C or above) without risking damage to BEOL structures, as the BEOL structures do not yet exist. The placeholder structure is prepared in advance to receive the high-temperature silicide formation process.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The FEOL process enables the formation of high-quality silicide layers at elevated temperatures, enhancing the connection performance of backside contact structures and reducing contact resistance, thus improving the overall performance of semiconductor devices.

Implementation Method 1

forming a silicide layer on the placeholder structure

Methodology Applied
Scientific EffectSilicidation: Chemical Bonding

Implementation Method 2

annealing temperature below the melting point of BEOL structures, thereby limiting the quality of the silicide layer

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentEP4633321A1Semiconductor device including backside contact structure with silicide layer formed in FEOL process
Publication Date: 2025.10.15 SAMSUNG ELECTRONICS CO LTD
  • EP4633321A1 patent drawingFigure 1A
  • EP4633321A1 patent drawingFigure 1B
  • EP4633321A1 patent drawingFigure 2

AI summary

Provided is a semiconductor device including a placeholder structure; a 1st silicide layer on a top surface of the placeholder structure; a 1st source/drain region on the 1st silicide layer; and a backside contact structure on a bottom surface of the placeholder structure. A method for manufacturing a semiconductor device includes: forming a channel structure on a substrate; forming a placeholder structure in the substrate; forming a silicide layer on the placeholder structure; forming a source/drain region on the silicide layer based on the channel structure; forming a gate structure on the channel structure; and forming a backside contact structure on a bottom surface of the placeholder structure.