Backside FEOL Thinning to Reduce Semiconductor Wafer Warpage
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Solution Overview
Problem
Semiconductor wafer bow and warpage during processing lead to alignment issues and inconsistent IC performance, reducing yield and increasing costs due to localized damage and inconsistent feature processing.
Innovation Solution
A method involving the concurrent formation of front end of line (FEOL) layers with specific thicknesses on both the frontside and backside of a semiconductor substrate, followed by reducing the thickness of the backside layers to mitigate wafer bow and warpage, thereby improving alignment precision and IC consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FEOL layers are formed on the frontside of the semiconductor substrate, then the functional circuit features are created, but wafer bow and warpage occur due to stress imbalance
Solution Approach 1:
The patent applies asymmetry by forming a first FEOL layer on the frontside and a second FEOL layer on the backside with different thicknesses. The backside layer thickness is specifically controlled to be less than the frontside layer thickness, creating an asymmetric stress distribution that compensates for the bow and warpage caused by frontside processing.
Solution Approach 2:
The patent changes the thickness parameter of the FEOL layers to control stress. By adjusting the thickness of the backside FEOL layer to be less than the frontside layer, the stress balance is modified to reduce wafer bow and warpage while maintaining the necessary functional features.
2Shape
If the backside FEOL layer thickness is reduced, then wafer bow and warpage are minimized, but the structural integrity may be compromised
Solution Approach 1:
The patent optimizes the thickness parameter of the backside FEOL layer within a specific range (50-200 nm) to achieve the right balance. This parameter control ensures the layer is thin enough to reduce stress-induced bow and warpage but thick enough to maintain structural integrity and provide stress compensation.
Solution Approach 2:
The patent applies local quality by forming the backside FEOL layer only in specific regions where stress compensation is needed, rather than uniformly across the entire backside. This localized approach maintains structural integrity in critical areas while reducing overall wafer bow and warpage.
Data Source
AI summary
Forming an integrated circuit, for example by first, concurrently forming a first front end of line (FEOL) layer having a first thickness and a surface contacting or facing a semiconductor substrate frontside and a second FEOL layer, having a second thickness and including a same material as the first FEOL layer and having a surface contacting or facing a semiconductor substrate backside, and second, processing the second FEOL layer to reduce the second thickness.