Backside Ferroelectric Capacitor Layout for Denser Memory Bitcells
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Solution Overview
Problem
The challenge in forming semiconductor devices, particularly non-volatile memory structures, lies in the difficulty of scaling down memory and logic cells due to the complexity of densely packing transistors, which limits the scalability of bitcells and storage density in integrated circuits.
Innovation Solution
The integration of ferroelectric capacitors in the backside interconnect structure, allowing for a self-aligned connection to frontend access transistors, reduces frontside routing overhead and enables relaxed dimensions and pitches, facilitating the creation of multi-capacitor bitcells with increased memory density through a staircase structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are packed more densely to scale down memory cells, then storage density increases, but the formation of memory structures becomes increasingly difficult and complex
Solution Approach 1:
The patent moves capacitor formation from the frontside to the backside of the semiconductor device, utilizing the vertical dimension and backside interconnect layers. This dimensional shift allows capacitors to be formed in a separate space from the densely packed frontside transistors, reducing formation complexity while maintaining high storage density through multi-plate capacitor structures in the backside interconnect.
2Ease of operation
If frontside routing is used to connect transistors to capacitors, then memory structures can be formed, but routing overhead increases and scaling is limited
Solution Approach 1:
Instead of routing from frontside transistors to frontside capacitors, the patent inverts the approach by placing capacitors on the backside and routing them through backside interconnect layers. This inversion eliminates the need for complex frontside routing through multiple interconnect layers, reducing routing overhead and enabling better scalability as transistors can be directly connected to backside capacitors through vertical vias.
3Quantity of substance
If capacitor dimensions are reduced to increase density, then storage capacity increases, but manufacturing precision requirements become more stringent
Solution Approach 1:
The patent employs multi-plate capacitor structures where multiple capacitor plates are nested within the backside interconnect layers. This nesting approach allows capacitors to share common electrodes and interconnect structures, effectively reducing the footprint per capacitor while maintaining adequate manufacturing tolerances. The shared infrastructure of backside interconnect layers provides a relaxed precision environment compared to frontside fabrication.
4Quantity of substance
If bitcell size is reduced to increase density, then storage capacity increases, but device spacing at the device layer becomes increasingly difficult to reduce
Solution Approach 1:
The patent relocates capacitor structures to the backside interconnect layers, effectively utilizing the vertical dimension and third spatial dimension (backside vs. frontside) to house memory components. This separation allows frontside device spacing to be optimized for transistor density while backside interconnect layers provide space for capacitors, enabling bitcell density improvement without further reducing already-minimal device spacing at the frontside device layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for further scaling of bitcells, significantly enhancing memory density by reducing the complexity of fabricating capacitors and enabling taller capacitors with multiple lateral plate connections, thereby improving the storage capacity of integrated circuits.
Implementation Method 1
a ferroelectric material layer between the first electrode and the second electrode
Data Source
AI summary
Backside integrated circuit capacitor structures. In an example, a capacitor structure includes a layer of ferroelectric material between first and second electrodes. The first electrode can be connected to a transistor terminal by a backside contact that extends downward from a bottom surface of the transistor terminal to the first electrode. The transistor terminal can be, for instance, a source or drain region, and the backside contact can be self-aligned with the source or drain region. The second electrode can be connected to a backside interconnect feature. In some cases, the capacitor has a height that extends through at least one backside interconnect layer. In some cases, the capacitor is a multi-plate capacitor in which the second conductor is one of a plurality of plate line conductors arranged in a staircase structure. The capacitor structure may be, for example, part of a non-volatile memory device or the cache of a processor.