Backside Ferroelectric Memory Cell Layout for Lower RC Delay
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices while maintaining performance and reducing costs, particularly in integrating high-density memory cells with efficient processing systems.
Innovation Solution
The integration of a backside ferroelectric capacitor with field effect transistors (FETs) to form a ferroelectric memory cell (FeRAM), which simplifies the fabrication process and enhances performance by reducing RC delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar MOSFETs and FinFETs are scaled down to increase storage capacity, then device density improves, but manufacturing process complexity increases
Solution Approach 1:
The patent implements a stacked three-dimensional memory architecture where memory cells are arranged vertically across multiple layers and levels. Memory arrays are formed in a stacked configuration with word lines extending in first directions and bit lines in second directions, creating a multi-dimensional memory structure that increases storage capacity without proportionally increasing manufacturing complexity
Solution Approach 2:
The memory device is divided into multiple independent memory blocks, each containing separate memory arrays with distinct word lines and bit lines. This segmentation allows for modular manufacturing and independent operation of memory blocks, reducing overall process complexity while maintaining high device density
2Area of stationary object
If memory cell dimensions are reduced to increase storage capacity, then area efficiency improves, but RC delays increase and performance deteriorates
Solution Approach 1:
By transitioning to a three-dimensional stacked architecture, the patent reduces the planar footprint of each memory cell while maintaining adequate signal path lengths. The vertical stacking allows smaller in-plane dimensions without proportionally reducing the conductive path lengths between word lines and bit lines, thereby reducing RC delays while improving area efficiency
Solution Approach 2:
The patent employs localized conductor routing where word lines and bit lines are positioned to optimize signal paths within each memory block. The interconnect structure is designed with specific attention to local routing quality, ensuring that despite reduced cell dimensions, the electrical paths maintain appropriate lengths and cross-sectional areas to minimize RC delays
Data Source
AI summary
A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.