Backside Ferroelectric Memory Cell Layout to Cut RC Delay
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor devices while maintaining performance and reducing costs, with complex manufacturing processes and inefficiencies in integrating logic with passive devices in ferroelectric memory cells.
Innovation Solution
A backside ferroelectric capacitor is stacked on field effect transistors to form an integrated ferroelectric memory cell, simplifying the fabrication process and reducing RC delays by creating a more compact design with direct connections between transistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional planar or finFET structures are used for scaling, then device density increases, but manufacturing complexity increases and integration with passive devices becomes inefficient
Solution Approach 1:
The patent transitions from planar (2D) and finFET (3D vertical) structures to a fully integrated 3D stacked architecture where transistors and capacitors are vertically stacked and bonded together. This dimensional change enables higher device density while simplifying manufacturing by integrating multiple components in the vertical dimension rather than requiring complex lateral scaling and separate passive device fabrication.
Solution Approach 2:
The patent merges previously separate active devices (transistors) and passive devices (capacitors) into a single integrated stacked structure. By bonding transistor substrates to capacitor substrates and forming direct electrical connections between source/drain regions and capacitor electrodes, the invention combines multiple components that were traditionally manufactured separately, thereby reducing overall manufacturing complexity and improving integration efficiency.
2Quantity of substance
If transistors and capacitors are integrated in conventional layouts, then storage capacity increases, but signal propagation distance increases causing higher RC delays
Solution Approach 1:
The patent uses vertical stacking to place capacitors directly above transistors in the third dimension, creating extremely short electrical connection paths. This vertical integration reduces signal propagation distance from lateral distances across the chip to minimal vertical distances through direct source/drain to electrode connections, thereby reducing RC delays while maintaining high storage capacity through increased vertical density.
Solution Approach 2:
The patent implements a nested structure where capacitor electrodes are positioned to overlap with transistor source/drain regions, and connection structures are nested within vias that extend through dielectric layers. This nesting minimizes the physical distance between functional elements and creates compact, efficient electrical pathways that reduce signal propagation delays.
Data Source
AI summary
A ferroelectric memory cell (FeRAM) is disclosed that includes an active device (e.g., a transistor) and a passive device (e.g., a ferroelectric capacitor) integrated in a substrate. The transistor and its gate contacts are formed on a front side of the substrate. A carrier wafer can be bonded to the active device to allow the active device to be inverted so that the passive device and associated contacts can be electrically coupled from a back side of the substrate.