Backside Film Warpage Control in Semiconductor Packages
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Solution Overview
Problem
Warpage control in semiconductor wafers and dies during wafer level packaging is a significant challenge due to thermal expansion differences between materials, leading to manufacturing process inefficiencies and potential package failure.
Innovation Solution
A semiconductor packaging method involving a carrier with a debond layer and dielectric layer, through interlayer vias, die attach, redistribution layers, and a backside film with higher thermal expansion coefficient and Young's modulus than the dielectric layer, which alleviates warpage by forming recesses and using controlled solder paste placement to reduce mechanical stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wafer level packaging is performed with semiconductor devices, then manufacturing efficiency is improved, but warpage control deteriorates due to thermal expansion differences between materials
Solution Approach 1:
The patent changes the physical-chemical parameters of the carrier substrate by selecting materials with specific thermal expansion coefficients and mechanical properties. The carrier is designed with a thermal expansion coefficient between 3-10 ppm/°C and Young's modulus between 70-150 GPa, which are optimized parameters to minimize warpage during thermal processing while maintaining manufacturing efficiency
Solution Approach 2:
The patent applies local quality by creating a carrier substrate with non-uniform structure - specifically, a glass substrate with a specific surface preparation on one side (the first surface) that contacts the semiconductor wafer, while the opposite side (second surface) has different properties. This localized differentiation allows the carrier to provide optimal support characteristics at the wafer interface while maintaining overall structural stability
2Adaptability or versatility
If materials with different thermal expansion coefficients are used in the package structure, then material compatibility is improved, but warpage during thermal processes worsens
Solution Approach 1:
The patent systematically controls the thermal expansion parameters of all materials in the package structure. The carrier substrate is specified with a thermal expansion coefficient of 3-10 ppm/°C, which is lower than typical organic substrates, to better match the semiconductor wafer and reduce differential thermal expansion. This parameter optimization allows material compatibility while minimizing warpage
Solution Approach 2:
The patent employs composite material structure by combining the glass carrier substrate with metal interconnect layers and dielectric materials. The glass substrate serves as a stable base with controlled thermal properties, while the composite structure of multiple layers (carrier, interconnects, dielectrics) is designed to balance thermal expansion forces, achieving both material compatibility and warpage control
3Strength
If the carrier substrate has high mechanical strength, then structural integrity is improved, but warpage control during thermal processes worsens due to stress
Solution Approach 1:
The patent optimizes the mechanical parameters of the carrier substrate by selecting glass materials with specific Young's modulus values (70-150 GPa) and thermal expansion coefficients (3-10 ppm/°C). These parameter changes balance the substrate's mechanical strength with its thermal response, ensuring structural integrity while reducing warpage through better thermal-mechanical compatibility
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces warpage during thermal processes, enhances manufacturing yield, and decreases costs by maintaining structural integrity and alignment accuracy through the use of a transparent backside film with controlled laser processing and selective solder paste placement.
Implementation Method 1
a backside film with higher thermal expansion coefficient and Young's modulus than the dielectric layer, which alleviates warpage
Implementation Method 2
A laser process is performed to form openings in the backside film and the dielectric layer to expose the TIVs
Data Source
AI summary
A semiconductor package and a manufacturing method for the semiconductor package are provided. The package comprises a die, through interlayer vias (TIVs), a dielectric film, a backside film and solder paste portions. The TIVs are disposed beside the semiconductor die and a molding compound laterally surrounds the die and the TIVs. The dielectric film is disposed on a backside of the semiconductor die, and the backside film is disposed on the dielectric film. The backside film has at least one of a coefficient of thermal expansion (CTE) and a Young's modulus larger than that of the dielectric film. The solder paste portions are disposed on the TIVs and located within openings penetrating through the dielectric film and the backside film. There is a recess located at an interface between the dielectric film and the backside film within the opening.