Backside Fin Processing for Threshold Voltage Tuning in FinFETs
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Solution Overview
Problem
Existing fin-based transistors face challenges in tuning device threshold voltage (Vt) and other characteristics due to diminishing dimensions of gate trench and fin-to-fin distance, and impurity implantation through the frontside can degrade mobility and affect performance.
Innovation Solution
Tuning transistor characteristics by processing the transistors from the backside of the integrated circuit, including backside sub-fin trimming, doping, and controlling dielectric materials to adjust vertical heights and impurity concentrations in lower regions of fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If impurity implantation is performed through the frontside to tune transistor characteristics, then threshold voltage control is achieved, but mobility degrades and performance is affected
Solution Approach 1:
The patent inverts the conventional frontside implantation approach by performing impurity implantation through the backside of the substrate. This allows tuning of transistor characteristics including threshold voltage without the harmful effects of frontside implantation on mobility and performance, as the implantation occurs from the opposite direction through the substrate thickness.
2Productivity
If gate trench and fin-to-fin distance are reduced to increase device density, then integration density improves, but tuning capability of transistor characteristics deteriorates
Solution Approach 1:
The patent transitions from two-dimensional frontside processing to three-dimensional backside processing through the substrate thickness. By implanting impurities through the backside at controlled depths, the invention enables characteristic tuning in the vertical dimension while maintaining high horizontal integration density, thus resolving the contradiction between density and tuning capability.
3Ease of manufacture
If uniform fin structure is used to simplify manufacturing, then manufacturing complexity is reduced, but precise control of transistor characteristics is limited
Solution Approach 1:
The patent applies local quality by creating vertically graded impurity concentrations within the fin structure through backside implantation. Different regions of the fin (upper vs. lower portions) receive different impurity concentrations, enabling precise local control of transistor characteristics while maintaining a relatively simple uniform fin geometry, thus achieving both manufacturing simplicity and characteristic precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise control of transistor characteristics such as threshold voltage, switching speed, and leakage current by avoiding adverse effects on the gate stack and upper regions, allowing for finer control of fin numbers and material interfaces.
Implementation Method 1
implanting impurities within the fin, through the bottom surface of the backside of the integrated circuit
Data Source
AI summary
An integrated circuit includes a first source region, a first drain region, a first fin having (i) a first upper region laterally between the first source region and the first drain region and (ii) a first lower region below the first upper region, and a first gate structure on at least top and side surfaces of the first upper region. The integrated circuit further includes a second source region, a second drain region, a second fin having (i) a second upper region laterally between the second source region and the second drain region and (ii) a second lower region below the second upper region, and a second gate structure on at least top and side surfaces of the second upper region. In an example, a first vertical height of the first lower region is different from a second vertical height of the second lower region by at least 2 nanometers (nm).