Backside FinFET Contact Structure for Lower Contact Capacitance
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Solution Overview
Problem
As semiconductor devices shrink in pitch size, there is a need to reduce capacitance between contacts to ensure electrical stability and improve performance.
Innovation Solution
The semiconductor device incorporates a back interlayer insulating film with back wiring lines, fin-type patterns, gate electrodes, source/drain patterns, and contact silicide films to enhance element performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If pitch size of the semiconductor device is decreased, then density is increased, but capacitance between contacts increases causing electrical instability
Solution Approach 1:
The patent introduces a vertical back contact structure that extends through the substrate to the back surface of the device. This three-dimensional contact architecture allows current to flow vertically through the substrate rather than horizontally through the pitch-constrained front surface, effectively adding a spatial dimension to the contact path and reducing the impact of pitch size on contact capacitance
Solution Approach 2:
The patent introduces a contact insulating liner as an intermediary layer between the back contact and the fin-type pattern. This liner layer, positioned at the interface between the contact and the active region, serves as an electrical insulator that prevents unwanted capacitance coupling between the back contact and the fin structure while maintaining the beneficial low-capacitance contact path
2Productivity
If gate length is not increased, then device scaling is maintained, but current control capability deteriorates
Solution Approach 1:
The patent transitions from a planar gate structure to a multi-gate structure where the gate electrode wraps around the fin-type pattern on multiple sides. This three-dimensional gate configuration increases the effective gate width without increasing the gate length, providing enhanced current control capability while maintaining aggressive scaling dimensions
Solution Approach 2:
The patent employs a multi-layer gate structure consisting of a gate insulating film and a gate electrode with potentially different material compositions. This composite gate structure optimizes both the electrical control characteristics and the mechanical properties, enabling effective current control in scaled devices
3Reliability
If multi-gate transistor structure is used, then current control capability is improved, but device complexity increases
Solution Approach 1:
The patent divides the channel region into multiple fin-type patterns that are spatially separated but electrically connected. This segmentation of the channel into discrete fin structures allows the gate to control current through multiple parallel paths, enhancing current control capability while enabling modular fabrication processes that manage device complexity
Data Source
AI summary
A semiconductor device includes a back interlayer insulating film, a back wiring line in the back interlayer insulating film, the back wiring line including a first surface and a second surface opposite the first surface in a first direction, a fin-type pattern on the first surface of the back wiring line and extending in a second direction, a gate electrode on the fin-type pattern and extending in a third direction, a first source/drain pattern on a first side of the gate electrode, the first source/drain pattern including a bottom surface contacting the fin-type pattern, a back source/drain contact in the fin-type pattern and connected to the first surface of the back wiring line, and a contact insulating liner between the fin-type pattern and the back source/drain contact, the contact insulating liner extending along at least a portion of side walls of the back source/drain contact.