Backside FinFET Contacts for Lower-Capacitance Interconnects
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to integrate high-performance, low-capacitance, and low-power devices within a single chip, while optimizing performance and addressing the limitations of traditional front-side connections in non-planar transistors.
Innovation Solution
The solution involves forming backside contacts and metallization on non-planar transistors, such as FinFETs, by using backside reveal processing, epitaxial deposition, and backside implantation to create flexible connections, allowing for efficient integration of devices with reduced capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional front-side connections are used in non-planar transistors, then manufacturing process is simpler, but device capacitance increases and performance decreases
Solution Approach 1:
The patent implements backside contacts that connect to the source and drain regions from the opposite side of the gate, inverting the traditional connection approach. This inversion reduces capacitance between the contact and gate by increasing spatial separation, thereby improving device performance while managing the added structural complexity through systematic process integration
2Reliability
If backside contacts are formed to reduce capacitance, then device performance improves, but manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary actions by forming the backside contacts and epitaxial structures before final device assembly and testing. The multi-step process including selective epitaxial growth, ion implantation, and controlled oxidation is executed in advance to establish low-capacitance connections, simplifying subsequent manufacturing steps while achieving performance goals
Solution Approach 2:
The fabrication process is segmented into distinct stages: selective epitaxial growth for contact formation, ion implantation for doping, and controlled oxidation for insulation. This segmentation allows each step to be optimized independently, managing overall process complexity while achieving the desired backside contact structure for improved device performance
3Quantity of substance
If device density is increased on chip, then capacity increases, but optimization of each device performance becomes more difficult
Solution Approach 1:
The patent applies local quality by implementing backside contacts specifically at critical source and drain regions where capacitance reduction is most needed for high-performance devices. This localized approach allows individual device optimization through reduced parasitic effects while maintaining high overall device density on the chip, as the enhancement is applied only where most beneficial
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-performance, low-capacitance devices with improved connectivity and reduced power consumption by utilizing backside connections, enhancing the integration density and performance of semiconductor chips.
Implementation Method 1
the carrier is removed to expose a second side of the fin
Implementation Method 2
an epitaxial material is introduced on the fin from a backside of the device
Implementation Method 3
an implant is introduced into the fin in source and drain regions from a backside of the device
Data Source
AI summary
An apparatus including a circuit structure including a device stratum including a plurality of devices including a first side and an opposite second side; and a metal interconnect coupled to at least one of the plurality of devices from the second side of the device stratum. A method including forming a transistor device including a channel between a source region and a drain region and a gate electrode on the channel defining a first side of the device; and forming an interconnect to one of the source region and the drain region from a second side of the device.