Backside FinFET Structure With Silicide Contact Reliability
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Solution Overview
Problem
Existing integrated circuit devices face challenges in achieving high integration and electrical reliability, particularly in the design and connectivity of field-effect transistors.
Innovation Solution
The integrated circuit device incorporates a back side interconnection structure with a fin-type active area, metal silicide film, and gate structures, featuring source/drain areas with insulating structures to enhance integration and reliability, including nanosheet stacks and insulating layers for improved electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backside contacts are used to improve integration, then device density increases, but electrical reliability deteriorates due to unstable connections
Solution Approach 1:
A metal silicide film is introduced as an intermediary layer between the backside contact and the active substrate. This intermediate layer provides stable electrical connection and improves reliability while maintaining the high integration benefits of backside contacts. The metal silicide film acts as a mediator that ensures reliable electrical connectivity without compromising device density.
Solution Approach 2:
The patent employs composite material structures combining different materials (metal silicide film with semiconductor substrate) to achieve both high integration and electrical reliability. The composite structure leverages the advantageous properties of each material - the conductivity of metal silicide and the semiconductor properties of the active substrate - to resolve the contradiction between integration and reliability.
2Device complexity
If source/drain areas directly contact the active substrate to simplify structure, then manufacturing complexity decreases, but electrical reliability deteriorates due to unstable connections
Solution Approach 1:
A metal silicide film is introduced as an intermediary layer between the backside contact and the active substrate. This intermediate layer provides stable electrical connection and improves reliability while maintaining the high integration benefits of backside contacts. The metal silicide film acts as a mediator that ensures reliable electrical connectivity without compromising device density.
3Manufacturing precision
If gate structures surround nanosheet stacks to improve transistor performance, then operational accuracy increases, but device complexity increases
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that surround the nanosheet stacks. This dimensional change enables superior electrical control and operational accuracy while the self-aligned fabrication process manages the increased structural complexity. The gate structures extend in multiple dimensions to provide all-around control of the channel.
Solution Approach 2:
The gate structure is segmented into multiple components including front gate, back gate, and side gates that collectively surround the nanosheet stacks. This segmentation allows independent optimization of each gate component while achieving comprehensive channel control. The segmented approach manages complexity by dividing the gate function into manageable, independently fabricable portions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances integration and electrical reliability of field-effect transistors by providing stable and efficient electrical connections, supporting high-performance semiconductor operations.
Implementation Method 1
A metal silicide film is between the back side interconnection structure and the active substrate
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
An integrated circuit device includes a back side interconnection structure extending in a first horizontal direction. An active substrate includes a fin-type active area extending in the first horizontal direction on the back side interconnection structure. A metal silicide film is between the back side interconnection structure and the active substrate. A plurality of gate structures extends in a second horizontal direction perpendicular to the first horizontal direction on the active substrate. A first source/drain area and a second source/drain area are spaced apart from each other in the first horizontal direction with the plurality of gate structures therebetween on the active substrate. The first source/drain area directly contacts the active substrate. The second source/drain area is spaced apart from the active substrate and insulated from the active substrate.