Backside Contact Gap Spacer for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor devices shrink, the close proximity of source/drain contacts and gate contacts reduces process windows and increases parasitic capacitance, impacting device performance and switching speed.
Innovation Solution
A method is developed to form a backside source/drain contact spaced apart from adjacent structures by a gap, involving the deposition of liners and a sacrificial spacer, followed by planarization to create a trench and seal plug, reducing parasitic capacitance between the contact and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backside contacts are placed in close proximity to gate structures to improve routing density, then device packing efficiency is improved, but parasitic capacitance increases and device performance deteriorates
Solution Approach 1:
A dielectric layer is introduced as an intermediary substance between the backside contact and the gate structure. This dielectric layer acts as a mediator that reduces the direct electrical interaction and parasitic capacitance between the contact and gate, while still allowing the routing to be in close proximity for high density.
Solution Approach 2:
The solution moves from a two-dimensional planar arrangement to a three-dimensional vertical stacking approach. By utilizing the vertical dimension with multiple layers (contact layer, dielectric layer, gate structure), the design achieves both high routing density through close proximity and low parasitic capacitance through vertical separation.
2Productivity
If feature dimensions are reduced to continue scaling, then device density increases, but process window decreases and manufacturing complexity increases
Solution Approach 1:
The structure is segmented into distinct functional layers: a backside contact layer, a dielectric layer, and a gate structure layer. This segmentation allows each layer to be optimized and manufactured independently with appropriate process windows, while achieving high overall device density through vertical integration.
Solution Approach 2:
By transitioning to three-dimensional vertical stacking, the design achieves higher device density without proportionally reducing lateral feature dimensions. This allows manufacturing processes to maintain larger process windows in the lateral direction while gaining density through the vertical dimension.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively reduces parasitic capacitance, improving device performance and switching speed by creating a low-dielectric constant gap between the backside contact and gate structures.
Implementation Method 1
Capacitance between the backside contacts and adjacent gate structures may impact device performance
Implementation Method 2
creating a low-dielectric constant gap between the backside contact and gate structures
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure include a source feature disposed over a backside source contact, a drain feature disposed over a backside dielectric layer, a plurality of channel members each extending between the source feature and the drain feature, and a gate structure wrapping around each of the plurality of channel members and disposed over the backside dielectric layer. The backside source contact is spaced apart from the backside dielectric layer by a gap.