Backside Programmable Gate Array for Faster PDN Customization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor fabrication methods face challenges in efficiently managing the power delivery network (PDN) as device densities increase, particularly in integrating backside power delivery networks, which requires iterative processes and long time-to-market for design changes.
Innovation Solution
The implementation of a backside programmable gate array structure, where placeholder vias are built on the backside of the wafer, allowing for customization of logic circuits by changing electrical contacts to these vias, enabling design changes without requiring new frontside masks, thus reducing time-to-market and allowing non-trusted foundries to complete bulk fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If backside power delivery network is integrated, then power delivery capability is improved, but manufacturing complexity increases due to iterative processes and long time-to-market for design changes
Solution Approach 1:
The patent segments the fabrication process into two independent parts: frontside processing (FEOL and frontside BEOL) and backside processing. The backside programmable gate array allows the backside PDN to be configured separately from the frontside transistor fabrication, enabling parallel processing and eliminating iterative re-fabrication cycles.
Solution Approach 2:
The placeholder vias are pre-formed during frontside fabrication before the final backside programming step. This preliminary action allows the frontside structures to be completed while leaving the backside connectivity flexible for later customization, reducing time-to-market for design changes.
2Adaptability or versatility
If design changes are made to backside power delivery network, then adaptability is improved, but time-to-market increases due to iterative fabrication processes
Solution Approach 1:
The backside programmable gate array introduces dynamic reconfigurability to the previously static PDN design. The ability to program different via configurations after frontside fabrication allows design adaptations without restarting the entire fabrication process, significantly reducing time-to-market for design changes.
Solution Approach 2:
Placeholder vias are created in advance during frontside fabrication, preparing the structure for future programming. This preliminary action enables rapid design changes on the backside without affecting the already-fabricated frontside structures, decoupling design iteration time from the full fabrication cycle.
3Productivity
If placeholder vias are built on backside, then customization efficiency is improved, but device complexity increases due to additional via structures
Solution Approach 1:
The placeholder vias serve multiple functions: they act as structural placeholders during frontside fabrication, serve as programming targets for backside customization, and ultimately become the programmed backside vias for final connectivity. This multi-functionality reduces the need for separate structures for each purpose.
Solution Approach 2:
The patent extracts the backside via programming step from the main fabrication sequence, making it a separate, optional customization phase. This allows the core fabrication process to remain simple while enabling complex customization only when needed, improving efficiency without permanently increasing base device complexity.
Data Source
AI summary
Embodiments of the present invention are directed to processing methods and resulting structures for integrated circuits having backside programmable gate arrays. In a non-limiting embodiment, a front end of line structure having an array of transistors is formed such that each transistor of the array of transistors includes one or more placeholder backside vias. A first portion of the backside vias defines one or more placeholder backside vias and a second portion of the one or more backside vias defines one or more programmed backside vias. A back end of line structure is formed on a first surface of the front end of line structure. A backside structure is formed on a second surface of the front end of line structure opposite the first surface. The backside structure includes a backside metallization layer in direct contact with the one or more programmed backside vias.