Backside Gate Contact Spacer Layout for Dense Semiconductor Isolation
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Solution Overview
Problem
As semiconductor device integration density increases, the reduced distance between gate and source/drain contact structures heightens the risk of short circuits, necessitating a solution to maintain device reliability and performance.
Innovation Solution
A backside gate contact structure is formed with a contact spacer that isolates it from the source/drain contact structure, reducing congestion and contact resistance, and allowing for self-aligned placement to prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the distance between gate contact structure and source/drain contact structure is reduced to increase integration density, then device integration density is improved, but the risk of short circuit between gate and source/drain contacts increases
Solution Approach 1:
The patent introduces a contact spacer structure that extends vertically from the substrate surface, creating a three-dimensional isolation barrier between the gate contact and source/drain contact. This vertical dimension approach allows horizontal proximity for high density while maintaining electrical isolation through the elevated spacer structure.
Solution Approach 2:
The contact spacer acts as an intermediary structure positioned between the gate contact structure and source/drain contact structure. This mediator provides physical and electrical isolation, enabling the two contacts to be placed closer together without risking short circuits, thus resolving the contradiction between density and reliability.
2Area of stationary object
If the distance between gate contact structure and source/drain contact structure is reduced, then area occupancy is improved, but contact resistance may increase due to congestion
Solution Approach 1:
By utilizing the vertical dimension with elevated contact spacers, the patent enables closer horizontal spacing of contacts without increasing congestion at the substrate level. This dimensional approach reduces area occupancy while maintaining low contact resistance through proper spatial separation.
Data Source
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AI summary
A semiconductor device includes: a 1st source/drain region; a 2nd source/drain region; a channel structure connecting the 1st source/drain region to the 2nd source/drain region; a gate structure configured to control the channel structure; a backside source/drain contact structure connected to a bottom surface of the 1st source/drain region; a backside isolation structure at a lower portion of the semiconductor device; and a 1st contact spacer on the backside source/drain contact structure, wherein the 1st contact spacer is configured to isolate the backside source/drain contact structure from another circuit element in the backside isolation structure.