Backside Gate Contact Widening for Low-Resistance Nanowire ICs
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits faces challenges due to variability in conventional fabrication processes, limiting further miniaturization beyond the 10 nanometer node, and requires new methodologies for efficient power delivery and contact formation to enhance performance and density.
Innovation Solution
The implementation of angled directional etching for widening backside gate or source/drain contact areas, allowing for larger contact areas and reduced resistance, and the integration of backside power delivery networks to alleviate space and performance constraints in semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for scaling multi-gate transistors, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability at 10 nanometer node and below
Solution Approach 1:
The fabrication process is divided into separate front-side and back-side operations. The backside contact formation is segmented as a distinct process stage, allowing independent optimization of contact dimensions without affecting front-side transistor fabrication precision.
Solution Approach 2:
The contact formation moves from the front-side two-dimensional plane to the back-side third dimension. This dimensional transition enables contact area enlargement through vertical cavity formation and lateral widening, achieving better electrical connection without compromising front-side feature precision.
2Area of stationary object
If front-side power routing is used, then power delivery is achieved, but device area increases due to extensive routing requirements
Solution Approach 1:
The power delivery approach is inverted by moving contact formation to the backside of the substrate. This reversal eliminates the need for long front-side power routing paths, reducing resistance while conserving chip area for functional devices.
Solution Approach 2:
Power delivery transitions from horizontal front-side routing to vertical backside contact formation. This dimensional change creates direct electrical pathways through the substrate, minimizing resistance without consuming lateral chip area.
3Reliability
If contact area is increased to reduce resistance, then electrical performance improves, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The backside contact cavity formation process is self-aligned to the transistor structure. The cavity automatically positions itself relative to the underlying devices through the substrate, eliminating the need for separate alignment operations and maintaining precision while enabling larger contact areas.
Solution Approach 2:
The substrate backside acts as an intermediary medium between the contact and the front-side devices. This intermediate layer enables large contact areas to be formed without direct lateral interaction with the sensitive front-side transistor features, decoupling contact size from alignment precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved electrical performance by reducing power network resistance, allowing for more compact designs, increased device density, and enhanced manufacturing efficiency by eliminating the need for extensive front-side power routing, thus addressing the limitations of current fabrication processes.
Implementation Method 1
The implementation of angled directional etching for widening backside gate or source/drain contact areas
Data Source
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AI summary
Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.