Backside Gate Cut Contact Layout for Dense Nanosheet Transistors
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Solution Overview
Problem
As nanosheet technology scales down, nanodevices become closer and interfere with each other, making it difficult to form connections to a backside power network.
Innovation Solution
A semiconductor device structure is developed with nanodevices arranged adjacent and parallel to each other, featuring a gate contact with a recessed portion and a backside gate cut dielectric pillar that extends through the recessed portion to directly contact the gate contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanodevices are scaled down and placed closer together, then device density and integration are improved, but interference between adjacent nanodevices increases and connection formation becomes more difficult
Solution Approach 1:
The gate contact structure is segmented into multiple portions (first gate contact portion, second gate contact portion, third gate contact portion) that are positioned at different locations and depths. This segmentation allows each portion to independently connect to different nanosheets without interfering with adjacent nanodevices, thereby maintaining high device density while reducing interference between closely spaced nanodevices.
2Length of moving object
If nanodevices are placed closer together, then pitch reduction is achieved, but forming connections to backside power network becomes more difficult
Solution Approach 1:
The gate contact structure utilizes vertical dimensionality by extending different gate contact portions to different depths and positions. The first gate contact portion connects to a first nanosheet at a first depth, the second gate contact portion connects to a second nanosheet at a second depth, and the third gate contact portion is positioned at a third location. This three-dimensional arrangement enables connection formation even when nanodevices are closely spaced, as connections are made in multiple spatial dimensions rather than being constrained to a single plane.
Data Source
AI summary
According to the embodiment of the present invention, a semiconductor device includes a plurality of nanodevices including a plurality of transistors. The plurality of nanodevices are located adjacent to and parallel to each other along an x-axis. A gate contact is located at an edge of a cell boundary between two nanodevices of the plurality of nanodevices. The gate contact includes a recessed portion. A backside gate cut dielectric pillar extends downwards through the recessed portion to be in direct contact with the gate contact.