Backside Gate Cut Structure for Overlay-Limited Semiconductor Gates
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Solution Overview
Problem
As semiconductor devices scale down, it becomes increasingly difficult to form gate cut features squarely on dielectric fins due to overlay and critical dimension uniformity limitations, leading to defects such as the gate cut feature missing the fin and cutting into the gate structure or channel region.
Innovation Solution
The method involves forming a gate cut feature from the backside of the substrate, extending through the gate structure, and self-aligning it to avoid mask misalignment, allowing for continued scaling while maintaining or increasing the process window without relying on dielectric fins or hybrid fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate cut features are formed using conventional frontside lithography and etch processes, then the gate cut features can be formed on dielectric fins, but mask alignment errors cause the top portion to miss the bottom portion, leading to defects
Solution Approach 1:
The patent forms the gate cut feature from the backside of the substrate rather than the frontside. This inversion of the formation direction enables self-alignment with the gate structure, eliminating mask overlay errors that occur in conventional frontside formation methods. The backside formation approach allows the gate cut feature to be precisely positioned without relying on mask alignment between multiple lithography steps.
Solution Approach 2:
The gate cut feature formation process utilizes the substrate's own backside surface and existing gate structure as references for self-alignment. The process inherently aligns the gate cut feature with the gate structure through the substrate's geometry and material properties, without requiring additional alignment marks or complex mask registration procedures.
2Productivity
If semiconductor devices are scaled down to smaller technology nodes, then production efficiency increases and costs decrease, but mask overlay precision becomes increasingly difficult to ensure
Solution Approach 1:
By inverting the gate cut feature formation to occur from the backside of the substrate, the patent eliminates the mask overlay precision requirements that become increasingly difficult to maintain at smaller technology nodes. This approach decouples the gate cut feature alignment from the frontside lithography process, allowing continued scaling without compromising alignment precision.
Solution Approach 2:
The self-aligning gate cut feature formation process automatically maintains precision at smaller technology nodes by using the substrate's backside and gate structure as inherent references. This self-service mechanism eliminates the need for increasingly precise mask overlay control as device dimensions shrink, enabling continued productivity improvements through scaling.
3Ease of manufacture
If gate cut features are formed using multiple sequential lithography and etch processes, then gate cut features can be created, but process complexity increases and process window decreases
Solution Approach 1:
The patent simplifies the manufacturing process by forming the gate cut feature from the backside in a single operation rather than through multiple sequential frontside lithography and etch steps. This inversion reduces process complexity and increases the process window by eliminating the need for multiple alignment-critical steps.
Solution Approach 2:
The self-aligning nature of the backside formation process inherently maintains precision without requiring complex process control. The process automatically adapts to variations in substrate and gate structure dimensions, maintaining a wide process window while simplifying the manufacturing steps required.
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.