Backside Gate Cut Structure for Gate Isolation in Scaled Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down, forming gate isolation features on hybrid fins from the front side becomes challenging due to overlay and critical dimension uniformity limitations, leading to defects and increased parasitic capacitance, which affects circuit speed and cross-talk coupling.
Innovation Solution
The method involves forming gate isolation features from the backside of the substrate, which self-aligns to avoid defects and extends through the gate structure, using air gaps to reduce parasitic capacitance by depositing dielectric materials in trenches and etching to create gate cut openings, thereby dividing the gate structure into segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If gate isolation features are formed from the front side, then the process aligns with conventional fabrication flows, but overlay and critical dimension uniformity limitations cause defects and increased parasitic capacitance
Solution Approach 1:
The patent inverts the conventional approach by forming gate isolation features from the backside of the substrate instead of the front side. This backside formation approach eliminates overlay and critical dimension uniformity limitations while maintaining compatibility with conventional fabrication flows, thereby resolving the technical contradiction between ease of manufacture and manufacturing precision
2Ease of manufacture
If gate isolation features are formed from the front side, then the process is simpler, but parasitic capacitance increases affecting circuit speed and cross-talk coupling
Solution Approach 1:
By forming gate isolation features from the backside, the patent achieves better isolation between gate structures, reducing parasitic capacitance and improving circuit speed while maintaining process simplicity through a modified but still straightforward fabrication approach
3Reliability
If dielectric fins are used for isolation, then isolation between gate structures is improved, but parasitic capacitance cannot be sufficiently reduced at smaller technology nodes
Solution Approach 1:
The patent forms gate isolation features that extend through the gate structure from the backside, creating a more effective isolation mechanism than conventional dielectric fins. This approach achieves superior isolation between gate structures while sufficiently reducing parasitic capacitance even at smaller technology nodes
Solution Approach 2:
The patent changes the formation approach and geometry of isolation features, transitioning from front-side dielectric fins to backside-formed gate isolation features that extend through the gate structure. This parameter change enables better isolation and lower parasitic capacitance at scaled technology nodes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach maintains or increases the process window for scaling down while reducing parasitic capacitance and improving isolation between gate structures, enhancing device performance by reducing effective dielectric constant and leakage.
Implementation Method 1
etching the isolation feature, thereby forming an opening exposing the hybrid fin at the backside of the workpiece, etching the hybrid fin, thereby extending the opening to a bottom surface of the metal cap layer
Implementation Method 2
depositing a dielectric material into the opening, thereby forming a gate isolation feature disposed between the first and second gate structures
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes channel members over a backside dielectric feature, a gate structure wrapping around the channel members, an epitaxial feature abutting the channel members, a first isolation feature disposed on a first sidewall of the gate structure and extending through the backside dielectric feature, and a second isolation feature disposed on a second sidewall of the gate structure and extending through the backside dielectric feature. A top surface of the first isolation feature is above a top surface of the second isolation feature.