Backside Gate Cut Formation for Semiconductor Scaling
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Solution Overview
Problem
As semiconductor devices scale down, it becomes increasingly difficult to form gate cut features squarely on dielectric fins due to overlay and critical dimension uniformity limitations, often resulting in defects such as cutting into the gate structure or channel region, especially with existing front-side processes that rely on mask alignment.
Innovation Solution
The process forms gate cut features from the back side of the substrate, extending through the gate structure without relying on dielectric fins, and is self-aligned to avoid mask misalignment issues, allowing for continued scaling while maintaining or increasing the process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If front-side lithography and etch processes are used to form gate cut features, then the gate cut features can be formed using existing manufacturing processes, but mask alignment errors cause the top portion to miss the bottom portion resulting in defects
Solution Approach 1:
The patent inverts the conventional approach by forming gate cut features from the backside of the substrate rather than the frontside. This reversal eliminates dependency on frontside mask alignment, as the backside process uses self-alignment to the gate structure, thereby resolving the overlay accuracy problem while maintaining ease of manufacture
Solution Approach 2:
The backside gate cut formation process is self-aligned to the gate structure, meaning the gate structure itself serves as the alignment reference. This self-service mechanism eliminates the need for separate mask alignment steps, automatically ensuring precise positioning of the gate cut features relative to the gate structure
2Productivity
If technology node scaling is pursued to increase functional density, then production efficiency improves and costs decrease, but mask overlay and critical dimension uniformity become increasingly difficult to ensure
Solution Approach 1:
By switching to backside gate cut formation, the patent removes the frontside mask alignment step that becomes increasingly problematic at smaller technology nodes. The self-aligned backside process maintains critical dimension uniformity even as feature sizes decrease, enabling continued scaling to improve functional density
Solution Approach 2:
The self-aligned nature of the backside process provides inherent process control that is less sensitive to dimensional variations. As technology nodes scale down, this self-service alignment mechanism maintains manufacturing precision better than conventional mask-based methods, supporting continued productivity improvement through scaling
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, a gate cut feature extending continuously from between the first gate structure and the second gate structure to between the first backside dielectric feature and the second backside dielectric feature, and a liner disposed between the gate cut feature and the first backside dielectric feature and between the gate cut feature and the second backside dielectric feature.