Backside Gate Cut Structure for Self-Aligned Semiconductor Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices scale down, it becomes increasingly difficult to form gate cut features squarely on dielectric fins due to overlay and critical dimension uniformity limitations, often resulting in defects such as the gate cut feature missing the fin and cutting into the gate structure or channel region.
Innovation Solution
The method involves forming a gate cut feature from the backside of the substrate, extending through the gate structure, and self-aligning it to avoid mask misalignment issues, allowing for continued scaling while maintaining or increasing the process window without relying on dielectric fins or hybrid fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If gate cut features are formed using sequential lithography and etch processes from the frontside, then the gate cut features can be formed on dielectric fins, but mask alignment errors cause the top portion to miss the bottom portion resulting in defects
Solution Approach 1:
The patent forms the gate cut feature from the backside of the substrate rather than the frontside. This inversion of the formation direction enables self-alignment with the gate structure, eliminating mask overlay errors that occur when forming features sequentially from the frontside. The backside formation approach allows the gate cut feature to be precisely positioned without relying on multiple lithography steps and mask alignments.
Solution Approach 2:
The gate cut feature formation process utilizes the substrate's own backside surface as the formation plane, enabling self-alignment with the gate structure. The process inherently aligns the gate cut feature with the gate structure below without requiring external alignment references or multiple lithography steps, thus eliminating mask overlay errors and improving both manufacturing precision and reliability.
2Ease of manufacture
If conventional frontside gate cut formation is used, then existing processes can be maintained, but mask overlay limitations prevent satisfactory alignment at smaller technology nodes
Solution Approach 1:
By inverting the formation direction to use the backside of the substrate, the patent eliminates the need for multiple frontside lithography steps and mask alignments. This approach maintains process simplicity while dramatically improving manufacturing precision, as the backside formation enables self-alignment that is not constrained by mask overlay limitations at smaller technology nodes.
Solution Approach 2:
The patent transitions from forming gate cut features in the planar dimension (frontside) to forming them from the vertical dimension (backside). This dimensional change allows the gate cut feature to be precisely positioned through self-alignment with the gate structure, eliminating mask overlay errors while maintaining ease of manufacture through a streamlined process.
3Productivity
If continuous gate structures are used, then device density is maintained, but gate cut features are needed to divide gates into segments for manufacturing purposes
Solution Approach 1:
By forming the gate cut feature from the backside, the patent simplifies the segmentation process while maintaining continuous gate structures on the frontside. The backside formation approach allows precise positioning of cut features without requiring complex frontside processing, thus maintaining device density while reducing manufacturing complexity.
Solution Approach 2:
The backside of the substrate serves as an intermediary plane for forming the gate cut feature, which then extends through to the frontside to segment the gate structure. This intermediary approach allows the gate to be divided into segments for manufacturing purposes while maintaining the appearance of continuous structures on the frontside, preserving device density without increasing visible complexity.
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a frontside and a backside. The workpiece includes a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, an isolation feature sandwiched between the first and second portions of the substrate. The method also includes forming a joint gate structure to wrap around each of the first and second pluralities of channel members, forming a pilot opening in the isolation feature, extending the pilot opening through the join gate structure to form a gate cut opening that separates the joint gate structure into a first gate structure and a second gate structure, and depositing a dielectric material into the gate cut opening to form a gate cut feature.