Backside Gate Etch Stop Layer for Damage-Free Stacked Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating stacked transistors with reduced feature sizes, where the integration of backside gate contacts damages channel regions and limits routing flexibility and device performance.
Innovation Solution
The implementation of a gate etch stop layer (ESL) made of high-k dielectric material, allowing backside gate contacts to be formed without damaging channel regions, enabling larger channel widths and improved routing flexibility by overlapping channel regions during the contact formation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If backside gate contacts are formed in conventional stacked transistor fabrication, then routing flexibility is improved, but channel regions are damaged during the contact formation process
Solution Approach 1:
A gate etch stop layer (ESL) is introduced as an intermediary layer between the gate electrode and the channel region. This ESL layer protects the channel region from damage during backside gate contact formation while allowing the contact to be formed through it. The ESL acts as a sacrificial protective layer that can be selectively removed or retained based on process requirements.
Solution Approach 2:
The gate etch stop layer is formed in advance before the backside gate contact formation process. This preliminary action ensures that the protective layer is already in place to prevent channel region damage during subsequent etching or contact formation steps.
2Speed
If channel region widths are increased to improve device speed, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is segmented into distinct steps with the gate etch stop layer serving as a reference plane for subsequent processing. This segmentation allows for independent optimization of channel width and contact formation, reducing overall fabrication complexity despite larger channel dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved device speed, increased routing flexibility, and enhanced process integration, with observed device speed improvements ranging from 14.4% to 19% by increasing channel region widths.
Implementation Method 1
a gate etch stop layer (ESL) made of high-k dielectric material, allowing backside gate contacts to be formed without damaging channel regions
Data Source
AI summary
A semiconductor device includes a backside gate etch stop layer (ESL) on a backside of a first gate stack, wherein a plurality of first nanostructures overlaps the backside gate ESL. The backside gate ESL may comprise a high-k dielectric material. The semiconductor device further includes the plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures over the plurality of first nanostructures and extending between second source/drain regions. A first gate stack is disposed around the plurality of first nanostructures, and a second gate stack over the first gate stack is disposed around the plurality of second nanostructures. A backside gate contact extends through the backside gate ESL to be electrically coupled to the first gate stack.