Backside Gate Etch Stop Layer for Low-Resistance Stacked Transistor Contacts
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Solution Overview
Problem
As the semiconductor industry advances towards increased device density, higher performance, and lower costs, challenges arise in the fabrication and design of stacked device configurations, such as stacking transistors, where reducing minimum feature sizes introduces additional complexities.
Innovation Solution
The implementation of a gate etch stop layer (ESL) on the backside of a lower gate stack in stacking transistors, made of metals like cobalt, titanium, or tungsten, allows for backside gate contacts to be formed without damaging the channel regions, enabling improved routing flexibility and increased device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If backside gate contacts are formed in stacked transistor configurations with reduced minimum feature sizes, then device density and integration are improved, but damage to channel regions and metal gate during contact formation increases
Solution Approach 1:
An etch stop layer is introduced as an intermediary component between the backside gate contact and the channel region. This layer selectively stops the etch process before it reaches the channel region, preventing damage while allowing contact formation. The etch stop layer acts as a protective mediator that enables the contact formation process without harming underlying sensitive structures.
Solution Approach 2:
The etch stop layer is formed in advance before the backside gate contact formation process. By preparing this protective layer beforehand, the design ensures that when etching occurs to create the contact, the channel region is already protected. This preliminary action prevents the need for complex in-process adjustments and ensures consistent protection against damage.
2Ease of manufacture
If backside gate contacts are formed with traditional approaches in stacked transistors, then contact formation is achieved, but aspect ratio of the contact becomes large leading to manufacturing difficulties
Solution Approach 1:
The solution introduces a vertical dimension to the contact structure by forming the backside gate contact through the etch stop layer rather than directly through the channel region. This dimensional approach allows the contact to be formed with a more favorable aspect ratio, as the etch stop layer provides a controlled path that reduces the vertical distance and complexity of the contact formation process.
3Reliability
If channel regions are protected from damage during backside gate contact formation, then device performance is improved, but routing flexibility is reduced
Solution Approach 1:
The etch stop layer serves as a mediator that decouples the constraint of channel region protection from routing flexibility. By providing a dedicated protective layer, the design allows backside gate contacts to be routed more flexibly without worrying about damaging the channel region, as the etch stop layer absorbs the protective function. This enables greater design freedom in contact placement and routing configurations.
Data Source
AI summary
A method includes forming a first transistor and a second transistor over a semiconductor substrate, wherein the first transistor and the second transistor are vertically stacked. The method further includes exposing a backside of a first gate stack of the first transistor; forming a backside gate etch stop layer (ESL) on the backside of the first gate stack; patterning a contact opening through the backside gate ESL to expose the first gate stack; and forming a backside gate contact in the contact opening. The backside gate contact extends through the backside gate ESL to electrically connect to the first gate stack.