Backside Gate Extension Layout for Stable Nanoscale Connections
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Solution Overview
Problem
As transistors with smaller physical dimensions are developed, the space for backside power rail connections and backside signal wire connections decreases, leading to potential loss of functionality or reduced performance due to weak and unstable connections.
Innovation Solution
The method involves forming a semiconductor structure with extended backside connections by creating a gate with a gate extension region, forming power rail connections in contact with the gate and outer shallow trench isolation material, and establishing a signal wire connection that is electrically isolated from other power rail connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If transistor physical dimensions are decreased, then processing speed and energy efficiency are improved, but space for backside power rail connections and backside signal wire connections decreases
Solution Approach 1:
The patent utilizes the backside of the transistor structure as an additional dimension for connections. By forming power rail connections and signal wire connections on the backside of the semiconductor substrate, the design moves connection space from the limited planar area to the vertical/third dimension, effectively increasing available connection area without increasing the transistor footprint.
Solution Approach 2:
The patent embeds multiple connection structures within the transistor body. The gate extension region is nested within the transistor structure, and power rail connections are formed within the substrate thickness. This nesting allows multiple functional elements to occupy overlapping or nested spatial regions, maximizing space utilization.
2Quantity of substance
If transistor physical dimensions are decreased, then transistor density is improved, but connection stability deteriorates
Solution Approach 1:
By moving connections to the backside of the substrate, the patent creates longer connection paths that can maintain stability even as device dimensions shrink. The extended gate region and backside connections provide mechanically robust attachment points that are less susceptible to the dimensional scaling effects that compromise connection stability in conventional planar designs.
Solution Approach 2:
The patent employs asymmetric connection routing where power rail connections and signal wire connections are differentially positioned and structured. The gate extension region extends asymmetrically to provide enhanced connection pathways, and signal wire spacers are positioned specifically to ensure stable electrical isolation and mechanical support for signal connections independent of power rail connections.
3Device complexity
If space for backside connections is decreased, then manufacturing complexity is reduced, but connection strength deteriorates
Solution Approach 1:
The patent divides the connection structure into distinct segmented components: outer shallow trench isolation material, inner shallow trench isolation material, gate extension region, signal wire spacers, and extended interlayer dielectric material. Each segment serves a specific function and can be independently formed and optimized, allowing complex connection functionality to be achieved through modular assembly rather than monolithic structure formation.
Solution Approach 2:
The patent introduces intermediate structures such as the gate extension region and signal wire spacers that mediate between the transistor active area and the backside connections. These intermediary elements provide transition zones that strengthen the connection pathway, distributing mechanical and electrical stress across multiple interfaces rather than relying on direct, potentially weak connections.
Data Source
AI summary
A semiconductor structure with extended backside connections is provided. In one embodiment, the semiconductor structure includes a set of backside source/drain contacts, wherein the set of backside source/drain contacts include a first backside source/drain contact, a second backside source/drain contact, and a third backside source/drain contact, a gate that includes a gate extension region, power rail connections that include a signal wire connection in contact with the gate extension region and a first interlayer dielectric, wherein the gate extension region extends from the gate to the signal wire connection, and wherein the signal wire connection is electrically isolated from the second backside source/drain contact and the third backside source/drain contact, and signal wire spacers disposed on sides of the signal wire connection, wherein the signal wire spacers are in contact with the first interlayer dielectric, an extended interlayer dielectric, the second backside source/drain contact, and the third backside source/drain contact.