Backside Cross-Coupled Gate Interconnects for Tight CPP Layouts
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Solution Overview
Problem
As transistor gate pitch shrinks, space between gate contacts and source/drain contacts decreases, leading to increased short circuit failures and challenging gate and gate contact placement due to limited component placement options, especially among source/drain contacts, which compete for available space.
Innovation Solution
Employing backside interconnects to connect gate structures laterally across the semiconductor device, utilizing sacrificial placeholders and backside gate contacts to form cross-coupled circuits within a two contacted poly pitch (CPP) region, allowing for efficient wire routing and preserving electrical integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor gate pitch shrinks to improve device density, then device density increases, but space between gate contacts and source/drain contacts decreases leading to increased short circuit failures
Solution Approach 1:
The patent introduces backside interconnects that route signals through the substrate from the backside to the frontside, adding a vertical dimension to the interconnect architecture. This allows gate contacts to be positioned further apart on the frontside while maintaining electrical connectivity through backside contacts, thereby reducing short circuit risks while preserving device density.
2Quantity of substance
If gate pitch shrinks to improve device density, then device density increases, but gate and gate contact placement becomes exceedingly difficult due to limited component placement options
Solution Approach 1:
By moving gate contact placement to the backside of the substrate, the patent creates additional placement options that are spatially separated from the frontside source/drain contacts. This vertical separation provides manufacturing engineers with more flexibility in positioning contacts without the same planar spacing constraints.
Solution Approach 2:
The patent divides the interconnect function into separate frontside and backside components. Gate contacts are placed on the backside while source/drain contacts remain on the frontside, segmenting the contact placement tasks into different spatial zones that can be independently optimized for manufacturing.
3Reliability
If source/drain contacts compete for available space to maintain device functionality, then device functionality is preserved, but layout area efficiency decreases
Solution Approach 1:
The patent relocates gate contacts to the backside of the substrate, freeing up frontside space that would otherwise be occupied by competing gate and source/drain contacts. This vertical redistribution of contacts maintains all necessary device functionalities while reducing the planar footprint and improving layout area efficiency by up to 7%.
Data Source
AI summary
A semiconductor device includes gate structures laterally disposed relative to one another across the semiconductor device. The row defines a frontside of the semiconductor device and a backside of the semiconductor device opposite the frontside. A cross-coupled circuit includes a first cross-couple connection connecting two gate structures on the frontside and a second cross-couple connection connecting two gate structures on the backside.