Backside Gate Isolation Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
As semiconductor technology advances towards smaller nodes, multi-gate MOSFETs face challenges in reducing parasitic capacitance between gate structures, which degrades device performance such as circuit speed and cross-talk coupling, even with low-k dielectric materials, and existing methods struggle to effectively enlarge the distance between adjacent gate structures for improved isolation.
Innovation Solution
The method involves forming gate isolation features from the backside of the substrate, which are self-aligned and extend through the gate structure, allowing for the trimming of gate electrodes to increase the distance between adjacent gate structures, thereby reducing parasitic capacitance. This process uses a combination of dielectric layers and etching techniques to create a seal layer that replaces dielectric fins, enhancing isolation without relying on high-resolution photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dielectric fins made of low-k dielectric material are used to provide isolation between gate structures, then isolation between gate structures is improved, but parasitic capacitance between gate structures cannot be sufficiently reduced
Solution Approach 1:
The patent transitions from two-dimensional planar isolation to three-dimensional gate isolation features that extend vertically from the substrate through the gate structure. This vertical extension into the third dimension enables greater isolation effectiveness and parasitic capacitance reduction without further lateral scaling
Solution Approach 2:
The patent inverts the conventional approach by forming isolation features from the backside of the substrate rather than from the frontside. This backside formation enables self-alignment with the gate structure and facilitates the vertical extension of isolation features through the gate, achieving superior isolation and parasitic capacitance reduction
2Object-generated harmful factors
If the distance between adjacent gate structures is increased to reduce parasitic capacitance, then parasitic capacitance is reduced, but device density and functional density decrease
Solution Approach 1:
The patent achieves greater separation distance between gate structures in the vertical dimension rather than lateral dimension. The gate isolation features extend vertically from the substrate through the gate structure, providing effective isolation and parasitic capacitance reduction while maintaining tight lateral spacing for high device density
3Manufacturing precision
If high-resolution photolithography is used to form gate isolation features with precise alignment, then manufacturing precision is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs self-aligned formation of gate isolation features where the isolation features automatically align with the gate structure during the formation process. The backside formation approach enables the isolation features to self-align with the gate structure without requiring high-resolution photolithography alignment, simplifying the fabrication process
Solution Approach 2:
The patent performs preliminary formation of gate isolation features from the backside of the substrate before final gate structure completion. This preliminary action establishes the isolation features in predetermined positions that automatically align with the subsequent gate structure formation, eliminating the need for high-resolution alignment
Data Source
AI summary
A semiconductor device includes a first channel member over a first backside dielectric feature, a first gate structure engaging the first channel member, a second channel member over a second backside dielectric feature, a second gate structure engaging the second channel member, and a first isolation feature includes a first portion laterally between the first and second backside dielectric features and a second portion laterally between the first and second gate structures. The first isolation feature is in physical contact with the first and second gate structures.