Backside Gate Isolation Structure for Scaled Semiconductor Cells
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Solution Overview
Problem
Existing CMG processes for forming gate isolation structures in semiconductor devices restrict further reduction of cell heights and processing window due to the use of dielectric fins, leading to defects such as work function shifts and TDDB failures.
Innovation Solution
Forming gate cut features from the backside of the substrate, independent of dielectric fins, to allow for further scaling-down and improved processing window, while avoiding defects associated with mask misalignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dielectric fins are used to form gate cut features from the front side, then gate isolation can be achieved, but cell height reduction is restricted and processing window narrows
Solution Approach 1:
The patent applies inversion by forming gate cut features from the backside of the substrate rather than the conventional front side. This approach removes the interference between gate cut features and dielectric fins, enabling independent formation of gate cuts and allowing further cell height reduction without compromising gate isolation precision.
Solution Approach 2:
The patent segments the gate electrode into multiple isolated segments by forming gate cut features that extend through the gate electrode from the backside. This segmentation achieves the required gate isolation while allowing the overall cell height to be reduced, as the gate cuts are formed independently from the dielectric fin structure.
2Manufacturing precision
If dielectric fins are used for gate cut formation, then gate isolation is achieved, but mask misalignment defects occur leading to work function shifts and TDDB failures
Solution Approach 1:
By inverting the formation approach to create gate cut features from the backside of the substrate, the patent eliminates the mask misalignment issues that occur with front-side formation. The backside formation process does not require precise mask alignment with front-side features, thereby preventing work function shifts and TDDB failures while maintaining gate isolation precision.
Solution Approach 2:
The patent extracts the gate cut formation process from the front-side photolithography and etch sequence that is susceptible to mask misalignment. By forming gate cuts from the backside using a separate process sequence, the patent removes the source of alignment defects and improves device reliability while preserving gate isolation precision.
3Manufacturing precision
If front side photolithography and etch processes are used to form gate cut features, then gate isolation can be achieved, but processing complexity increases and processing window decreases
Solution Approach 1:
The patent simplifies the processing by inverting the gate cut formation to the backside of the substrate. This approach eliminates the need for complex front-side photolithography and etch sequences, reducing processing steps and expanding the processing window while maintaining gate isolation precision through the alternative backside formation methodology.
Data Source
AI summary
A semiconductor structure includes a gate structure disposed over a channel region, a first source/drain feature and a second source/drain feature adjacent to the gate structure, and a gate isolation structure extending through the gate structure and disposed between the first source/drain feature and the second source/drain feature along a direction. The gate isolation structure comprises a bottom portion and a top portion above the bottom portion, the bottom portion is disposed below the gate structure, the first source/drain feature, and the second source/drain feature, and the top portion comprises an air gap sandwiched by the gate structure.