Backside Gate Isolation Structure for Scaled Semiconductor Cells
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Solution Overview
Problem
Existing cut metal gate (CMG) processes in semiconductor fabrication are limited by the use of dielectric fins, which restrict the ability to further reduce cell heights and maintain a reasonable processing window, leading to defects and performance issues.
Innovation Solution
The proposed solution involves forming gate cut features from the backside of the substrate, eliminating the need for dielectric fins and allowing for independent gate isolation, thereby enabling further scaling down of cell heights and increasing the processing window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dielectric fins are used to form gate cut features, then gate isolation can be achieved, but cell height reduction is restricted and processing window becomes unreasonable
Solution Approach 1:
The patent forms gate cut features from the backside of the substrate rather than from the front side. This inversion of the formation direction eliminates the need for dielectric fins and allows gate cut features to be formed independently, enabling further cell height reduction while maintaining reasonable processing windows
Solution Approach 2:
The patent transitions from forming gate cut features in the lateral dimension (from front side) to forming them in the vertical dimension (from backside through the substrate). This dimensional change allows gate cut features to be formed without occupying lateral space, enabling better scaling
2Manufacturing precision
If dielectric fins are used for gate cut features, then gate segmentation is achieved, but processing window becomes unreasonable
Solution Approach 1:
By inverting the formation direction to backside processing, the patent achieves gate segmentation without the constraints of front-side dielectric fin formation, thereby maintaining a reasonable processing window
3Manufacturing precision
If dielectric fins are used, then gate cut features can be formed, but cell height reduction is restricted
Solution Approach 1:
The backside formation approach allows gate cut features to be created without the lateral space requirements of dielectric fins, enabling continued cell height reduction
Solution Approach 2:
Moving the formation process to the vertical dimension from the backside allows gate cut features to be formed without consuming lateral cell height, enabling further scaling
Data Source
AI summary
A semiconductor device includes a first dielectric layer, a stack of semiconductor layers disposed over the first dielectric layer, a gate structure wrapping around each of the semiconductor layers and extending lengthwise along a direction, and a dielectric fin structure and an isolation structure disposed on opposite sides of the stack of semiconductor layers and embedded in the gate structure. The dielectric fin structure has a first width along the direction smaller than a second width of the isolation structure along the direction. The isolation structure includes a second dielectric layer extending through the gate structure and the first dielectric layer, and a third dielectric layer extending through the first dielectric layer and disposed on a bottom surface of the gate structure and a sidewall of the first dielectric layer.