Backside Gate Jumper Layout for Tighter Transistor Cell Scaling
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Solution Overview
Problem
The challenge of scaling down transistor dimensions and spacing to fit a larger number of transistors on a chip is hindered by limitations in reducing epi-epi spacing to avoid shorts and metal layer congestion, which affects the ability to minimize cell height.
Innovation Solution
Implementing a dielectric wall to electrically isolate adjacent epi layers and a backside bridge to couple gates, allowing closer spacing of diffusion regions while maintaining electrical continuity, and relocating power distribution to backside layers to reduce topside routing congestion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If epi-epi spacing is reduced to scale down transistor dimensions, then the number of transistors that can be fitted on the chip increases, but the risk of epi-epi shorts increases
Solution Approach 1:
The gate is segmented into multiple gates (first gate and second gate) separated by a dielectric wall, allowing adjacent epi layers to be electrically isolated while maintaining close physical spacing. This segmentation enables reduced epi-epi spacing without increasing short risk.
Solution Approach 2:
A dielectric wall is introduced as an intermediary structure between adjacent epi layers to provide electrical isolation. This mediator allows the epi layers to be spaced closer together while preventing shorts, resolving the contradiction between density and reliability.
2Area of moving object
If epi-epi spacing is reduced to minimize cell height, then the chip area utilization improves, but metal layer congestion increases
Solution Approach 1:
The power distribution network is moved from the topside (2D plane) to the backside of the chip, utilizing the third dimension (vertical stacking). This dimensional change reduces topside routing congestion while enabling minimized cell height.
Solution Approach 2:
Instead of routing power distribution on the conventional topside, the approach inverts the routing strategy by placing power distribution on the backside of the chip. This inversion reduces metal layer congestion on the active circuit layer.
3Quantity of substance
If transistor dimensions are scaled down to fit more transistors on the chip, then the chip capacity increases, but the manufacturing precision requirements increase
Solution Approach 1:
The gate is divided into multiple segments (first gate and second gate) with a dielectric wall in between. This segmentation allows each gate segment to be manufactured independently with relaxed precision requirements, while achieving the overall effect of high-density transistor placement.
Data Source
AI summary
A chip includes one or more first channels extending in a first direction, a first epitaxial (epi) layer coupled to the one or more first channels, a first gate, wherein the one or more first channels pass through the first gate, one or more second channels extending in the first direction, a second epi layer coupled to the one or more second channels, and a second gate, wherein the one or more second channels pass through the second gate. The chip also includes a dielectric wall extending in the first direction, wherein the dielectric wall is disposed between the first epi layer and the second epi layer, and the dielectric wall is disposed between the first gate and the second gate. The chip further includes a backside bridge underneath the first gate and the second gate, wherein the backside bridge couples the first gate and the second gate.