Back-Side Gate Isolation Structure for Scaled MOSFET Integration
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Solution Overview
Problem
The miniaturization of metal-oxide-semiconductor field-effect transistors (MOS-FETs) in semiconductor devices compromises operational characteristics, necessitating improvements in electrical performance and integration density.
Innovation Solution
A semiconductor device design incorporating first and second transistors on a substrate with an isolation transistor between them, a lower power line in the substrate, and back-side gate contacts connecting to dummy gate electrodes, enhancing electrical characteristics and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOS-FETs are scaled down to increase integration density, then integration density is improved, but operational characteristics deteriorate
Solution Approach 1:
The patent introduces back-side gate contacts that penetrate through the substrate from the rear surface, adding a vertical dimension to the gate control structure. This allows the gate electrode to extend from both the front surface (conventional gate) and the back surface (back-side gate contact), creating a three-dimensional gate configuration that enhances control over the channel without increasing the planar footprint, thus improving operational characteristics while maintaining integration density.
Solution Approach 2:
The gate electrode is configured to extend from both the front surface and the back surface of the substrate, with the back-side gate contact penetrating through the substrate to connect to the gate electrode. This nested structure allows the gate control to be embedded within the substrate thickness, effectively utilizing the vertical space to enhance transistor control without occupying additional lateral area.
2Quantity of substance
If transistors are miniaturized to improve integration density, then integration density is improved, but electrical performance deteriorates
Solution Approach 1:
By extending the gate electrode through the substrate and making contact from the back surface, the patent creates a multi-dimensional gate structure that provides enhanced electrostatic control over the miniaturized transistor channel. This vertical extension compensates for the reduced lateral dimensions, maintaining electrical performance despite transistor miniaturization.
Solution Approach 2:
The gate control is divided into two segments: the conventional gate electrode on the front surface and the back-side gate contact on the rear surface. This segmentation allows independent optimization of each gate segment, with the back-side gate contact providing additional control that compensates for the effects of miniaturization on the main gate.
3Reliability
If isolation transistors are added between transistors to improve electrical characteristics, then electrical performance is improved, but device complexity increases
Solution Approach 1:
The back-side gate contact structure serves multiple functions: it provides gate control for the main transistors and simultaneously acts as an isolation mechanism between adjacent transistors. By controlling the potential of the gate electrode through the back-side contact, the patent can electrically isolate transistors without requiring additional isolation structures, thus reducing device complexity while maintaining electrical performance.
Solution Approach 2:
The patent combines the gate control function and the isolation function into a single structural element—the back-side gate contact. Instead of having separate isolation structures between transistors, the gate electrode extended through the substrate serves both to control the channel and to provide electrical isolation when appropriately biased, simplifying the overall device structure.
Data Source
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AI summary
A semiconductor device including: first and second transistors on a substrate; an isolation transistor provided between the first and second transistors; a lower power line in a lower portion of the substrate; and a back-side gate contact penetrating the substrate and connected to the lower power line and a dummy gate electrode of the isolation transistor.