Self-Aligned Backside Gate Contacts for Nanosheet Overlay Limits
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Solution Overview
Problem
Forming direct backside contacts (DBC) in semiconductor devices is challenging due to lithography overlay issues and high aspect ratio etch processes, especially as contacted poly pitch becomes smaller, leading to patterning difficulties and voids, particularly when connecting to gate structures from the backside of nanosheet channels.
Innovation Solution
The implementation of self-aligned backside gate contact structures using a varying-height silicon germanium stop layer and silicon nitride capping patterns aligned with channel structures, allowing for the formation of a backside gate placeholder element that is self-aligned, facilitating the connection between the backside power distribution network and gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If direct backside contacts (DBC) are formed using conventional lithography and etch processes, then power delivery efficiency can be improved, but patterning difficulties and voids occur due to high aspect ratio etch processes and lithography overlay issues
Solution Approach 1:
The patent applies preliminary action by forming placeholder elements at the backside contact locations before the actual gate contact formation. These placeholders serve as pre-positioned alignment references that guide subsequent etching and contact formation processes, ensuring precise patterning without relying on high-precision lithography overlay at critical stages.
Solution Approach 2:
The patent introduces placeholder elements as intermediary structures that mediate between the backside power distribution network and the gate structures. These placeholders act as temporary alignment markers and etch stop references, enabling precise contact formation while avoiding the direct high-precision alignment challenges between lithography patterns and etch features.
2Productivity
If contacted poly pitch is reduced to improve device scaling, then device density increases, but patterning difficulties and voids increase due to high aspect ratio etch processes
Solution Approach 1:
The placeholder elements are formed in advance at the reduced pitch locations, providing pre-established alignment references that enable subsequent processing to proceed without requiring high-precision lithography at each stage. This preliminary positioning allows device scaling to reduced pitch while maintaining patterning ease through self-alignment to the placeholders.
3Manufacturing precision
If self-aligned backside gate contact structures are formed using placeholder elements, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The placeholder elements enable self-alignment for the backside gate contacts. The contacts automatically align to the gate structures by using the placeholders as reference markers, eliminating the need for complex external alignment procedures and high-precision lithography overlay control. The structure serves its own alignment function.
Data Source
AI summary
A method of fabricating a semiconductor device includes forming capping patterns that are spaced apart in a first direction on a second side of a semiconductor structure, and forming channel structures that are spaced apart in the first direction on a first side of the semiconductor structure. A bottom portion of a gate structure extends between first and second channel structures among the channel structures. The first and second channel structures vertically overlap first and second capping patterns among the capping patterns, respectively. The method further includes forming a backside gate contact structure that contacts the bottom portion of the gate structure and is aligned based on the first and second capping patterns.