Backside Gate Rail Layout for Low-Resistance FinFET Gates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor manufacturing is to reduce gate resistance while minimizing parasitic capacitance, which is crucial for improving the performance of semiconductor devices such as RF devices and FinFETs.
Innovation Solution
The implementation of a backside gate rail structure that is electrically connected to the gate structures through backside gate vias, reducing the overlap area with source/drain structures and thereby minimizing parasitic capacitance, while also allowing for reduced gate resistance by applying gate voltage to both gate conductive lines and the backside gate rail.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate conductive lines are extended to reduce gate resistance, then gate resistance decreases, but parasitic capacitance increases due to increased overlap area with source/drain structures
Solution Approach 1:
The patent introduces a backside gate rail structure that extends the gate conductive line to the backside of the semiconductor device. By utilizing the vertical dimension and routing the gate rail underneath the source/drain structures, the gate resistance is reduced without increasing the planar overlap area, thereby minimizing parasitic capacitance.
Solution Approach 2:
The gate conductive path is segmented into two parts: a frontside gate conductive line that interfaces with the gate structure, and a backside gate rail that extends underneath the source/drain structures. This segmentation allows the gate resistance to be reduced through the extended backside rail while the frontside overlap area remains minimal, preventing parasitic capacitance increase.
2Productivity
If geometry size is scaled down to increase functional density, then production efficiency increases, but manufacturing complexity increases
Solution Approach 1:
The backside gate rail structure utilizes the vertical dimension by routing gate conductors underneath the source/drain structures. This three-dimensional arrangement allows for reduced gate resistance in scaled-down devices without requiring proportionally smaller feature sizes, thereby maintaining manufacturing feasibility while achieving higher functional density.
Data Source
AI summary
A device includes a first transistor, a second transistor, an interlayer dielectric (ILD) layer, and a backside gate rail. The first and second transistors are arranged along a first direction in a top view. The first transistor includes a first channel layer, a gate structure surrounding the first channel layer, a first source/drain epitaxial structure and a second source/drain epitaxial structure connected to the first channel layer. The second transistor includes a second channel layer, the gate structure surrounding the second channel layer, a third source/drain epitaxial structure and a fourth source/drain epitaxial structure connected to the second channel layer. A portion of the ILD layer is sandwiched between the first and third source/drain epitaxial structures. The backside gate rail is under the ILD layer and is electrically connected to the gate structure. The portion of the ILD layer is directly above the backside gate rail.