Backside Gate Contact Layout for Lower Front-Side Routing Density
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Solution Overview
Problem
The challenge in integrated circuits is to increase computing power while minimizing routing density at the front side, which is essential for miniaturization and reducing current leakage or short-circuits between metal lines.
Innovation Solution
The solution involves forming backside metal gate plugs and backside source/drain plugs at the backside of the integrated circuit, allowing for metal routing to be performed at the backside. This reduces routing density at the front side, facilitating miniaturization and preventing current leakage or short-circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal routing is performed at the front side of the integrated circuit, then connectivity and signal transmission are achieved, but routing density increases which prevents miniaturization and causes current leakage or short-circuits between metal lines
Solution Approach 1:
The patent applies dimensionality change by moving metal routing from the front side (2D plane) to the backside of the integrated circuit (3D space utilization). This allows routing to occur in an additional spatial dimension, reducing congestion and density on the front side while maintaining connectivity. The backside routing layers provide extra space for metal traces, thereby preventing current leakage and short-circuits without increasing overall routing density.
2Productivity
If the number of transistors and integrated circuit features is increased for a given area, then computing power increases, but routing density increases which prevents further miniaturization
Solution Approach 1:
By utilizing the backside of the integrated circuit for metal routing, the patent creates additional routing capacity without occupying front-side space where transistors and active features are located. This enables higher transistor density and computing power on the front side while routing complexity is managed on the backside, effectively decoupling the two constraints and enabling further miniaturization.
3Area of moving object
If routing density at the front side is reduced to enable miniaturization, then device size decreases, but connectivity and signal transmission must be maintained
Solution Approach 1:
The patent resolves this contradiction by relocating routing operations to the backside of the device, utilizing the third dimension (depth/thickness) to maintain connectivity without occupying front-side area. This allows the device to be miniaturized on the front plane while the backside provides sufficient space for all necessary metal routing and interconnections, thereby maintaining ease of operation regarding connectivity.
Solution Approach 2:
The patent segments the routing function into front-side and back-side layers, with the backside carrying the majority of metal routing traffic. This segmentation allows the front side to be optimized for miniaturization with minimal routing, while the backside handles the complex interconnect requirements, ensuring both miniaturization and connectivity are achieved.
Data Source
AI summary
An integrated circuit includes a substrate at a front side of the integrated circuit. A first gate all around transistor is disposed on the substrate. The first gate all around transistor includes a channel region including at least one semiconductor nanostructure, source/drain regions arranged at opposite sides of the channel region, and a gate electrode. A shallow trench isolation region extends into the integrated circuit from the backside. A backside gate plug extends into the integrated circuit from the backside and contacts the gate electrode of the first gate all around transistor. The backside gate plug laterally contacts the shallow trench isolation region at the backside of the integrated circuit.