Self-Aligned Backside Gate Contact for Shared FET Connections
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices require extra space for gate cuts between nFET and pFET connections, leading to non-optimal integrated circuit configurations.
Innovation Solution
A self-aligned backside contact is shared between gates of two FETs, extending across shallow trench isolation and backside interlayer dielectric, with a continuous profile from frontside to backside, allowing for a larger contact area without additional space requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate gate contacts are used for nFET and pFET connections, then each transistor can be independently connected, but extra space is required for gate cuts between the transistors
Solution Approach 1:
The patent merges the gate contacts of nFET and pFET into a single shared backside contact structure. Instead of providing separate gate contacts for each transistor type, the invention combines them into one common contact that serves both nFET and pFET gates, thereby eliminating the need for separate gate cut spaces while maintaining reliable electrical connections to both transistor types.
Solution Approach 2:
The patent transitions from a planar gate contact arrangement to a three-dimensional configuration by placing the gate contact on the backside of the substrate. This dimensional change allows the gate contact to be positioned beneath the transistor structures, eliminating the need for lateral gate cuts and reducing the horizontal space required on the chip surface.
2Reliability
If larger contact area is used for backside contact, then connection reliability improves, but additional space requirements increase
Solution Approach 1:
By moving the contact to the backside of the substrate and utilizing the vertical dimension, the patent enables a larger contact area without increasing the chip's horizontal footprint. The backside contact can extend vertically and laterally in a manner that provides enhanced connection reliability while actually reducing the overall space consumed on the chip surface.
Solution Approach 2:
The backside contact structure is designed to nest within the existing substrate and interlayer dielectric architecture. The contact extends through the substrate thickness and integrates with the three-dimensional stacking of interlayer dielectric layers, allowing a large effective contact area without proportionally increasing the horizontal space occupation.
3Area of stationary object
If self-aligned backside contact is implemented, then space efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary actions during the substrate preparation and initial processing stages to pre-position the backside contact structure. By establishing the contact alignment and positioning early in the fabrication process, before subsequent layers are deposited, the need for complex realignment operations later is reduced, thereby managing manufacturing complexity while achieving space efficiency.
Solution Approach 2:
The self-aligned nature of the backside contact allows the structure to automatically position itself relative to the transistor features through the inherent geometry of the substrate and processing steps. The contact alignment is achieved through self-reference to the substrate edges or pre-formed features, eliminating the need for additional complex alignment operations and reducing overall fabrication complexity.
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a first field effect transistor (FET) region, a second FET region and a backside signal distribution network (BSSDN). The first FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends through the STI and the ILD. The second FET region includes a substrate, interlayer dielectric (ILD), shallow trench isolation (STI) disposed in the substrate and a contact that extends to the STI. The BSSDN is disposed on the ILD in the first and second regions to contact with the contact in the first FET region.