Backside Gate Contact Structure for Short-Channel Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in scaling density and improving device performance and reliability, particularly with multi-gate transistors, where current control and short channel effects are not adequately addressed.
Innovation Solution
The semiconductor device incorporates a design with first and second channel patterns surrounded by a gate structure, featuring a gate insulating film and gate electrode, and includes backside and frontside gate contacts with specific inclined surfaces and dimensions, enhancing current control and reducing short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used to increase device density, then device density is improved, but short channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional multi-gate structures (FinFET, nanowire, or nanosheet configurations) where the gate electrode wraps around the channel in multiple directions. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short channel effects while enabling higher device density through vertical stacking and three-dimensional channel geometries.
Solution Approach 2:
The gate electrode is positioned to surround and enclose the channel structure in a nested configuration, with the gate wrapping around the channel from multiple sides. This nested arrangement maximizes the gate's electrostatic control over the channel region, preventing drain-induced barrier lowering and other short channel effects that plague planar devices.
2Reliability
If gate contact area is increased to improve electrical connection, then contact reliability is improved, but device area is increased
Solution Approach 1:
The gate contact structure extends vertically through the gate insulating film to reach the gate electrode, creating a three-dimensional contact path rather than a simple planar interface. This vertical extension increases the effective contact area and electrical connection reliability without proportionally increasing the lateral device footprint, as the contact benefits from the third dimension (depth/vertical direction).
Data Source
AI summary
There is provided a semiconductor device that can improve device performance and reliability. The semiconductor includes a first channel pattern and a second channel pattern spaced apart in a first direction, a gate structure surrounding the first and second channel patterns, extending in a second direction, and including a gate insulating film and a gate electrode, and a backside gate contact penetrating the gate insulating film and including a contact surface that contacts the gate electrode, wherein the gate electrode has a first surface and a second surface opposite to each other in the first direction, the gate insulating film extends along the first surface of the gate electrode, and in a cross-sectional view in the second direction, the contact surface of the backside gate contact includes a first inclined flat surface and a second inclined flat surface that are inclined with respect to the first direction.