Backside Gate Line Slit Structure for 3D Memory Wafer Bow Reduction
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Solution Overview
Problem
As 3D memory architectures increase in vertical layers, wafer bow, thermal stress, contamination, and overlay and bonding misalignments become significant challenges, limiting manufacturing efficiency, yield, and scalability.
Innovation Solution
Implementing a backside gate line slit in 3D memory devices to reduce wafer bow and thermal stress, minimize contamination, and improve overlay alignment by patterning the gate line slit on the backside of the memory array device after bonding the peripheral device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of 3D memory layers is increased to improve memory density, then memory density is improved, but wafer bow increases
Solution Approach 1:
The gate line structure is segmented by introducing slits that divide the continuous gate line into multiple sections. This segmentation allows the gate line to accommodate thermal expansion and stress more effectively, reducing wafer bow while maintaining high memory density through the 3D vertical architecture.
Solution Approach 2:
The gate line structure transitions from uniform to non-uniform by introducing slits at specific locations. These localized modifications create regions of reduced stiffness that allow for stress relief, enabling the overall structure to maintain flatness despite the increased number of memory layers.
2Quantity of substance
If the number of 3D memory layers is increased to improve memory density, then memory density is improved, but thermal stress increases
Solution Approach 1:
The continuous gate line is divided into segmented sections by slits, creating expansion joints that can accommodate thermal stress. This segmentation prevents stress accumulation across the entire wafer, allowing higher memory density without excessive thermal stress buildup.
Solution Approach 2:
The gate line structure's mechanical properties are modified by introducing slits, changing its flexibility and stress distribution characteristics. This parameter change enables the structure to better withstand thermal stress while maintaining the vertical stacking needed for high memory density.
3Quantity of substance
If the number of 3D memory layers is increased to improve memory density, then memory density is improved, but overlay and bonding misalignments increase
Solution Approach 1:
The gate line structure is modified locally by adding slits at strategic positions that serve as alignment references. These localized features provide precise registration points for overlay patterning and bonding processes, improving manufacturing precision while enabling higher memory density through vertical stacking.
4Manufacturing precision
If wafer bow is decreased to improve bonding alignment, then bonding misalignment is improved, but device complexity increases
Solution Approach 1:
Rather than modifying the entire wafer structure to reduce bow, the gate line is segmented with slits, providing a localized solution that achieves bonding alignment improvement without substantially increasing overall device complexity. The segmentation is integrated into the existing gate line formation process.
Data Source
AI summary
A three-dimensional (3D) memory device includes a memory array device, a peripheral device, an etch stop layer, and a backside gate line slit. The memory array device includes a frontside and a backside, a plurality of memory strings, and a plurality of word lines in a staircase structure coupled to the plurality of memory strings. The peripheral device is above the frontside of the memory array device. The etch stop layer is between the memory array device and the peripheral device. The backside gate line slit extends through the backside of the memory array device to the etch stop layer. The backside gate line slit includes a conductive gate line layer and an insulating gate line layer. The 3D memory device can increase manufacturing efficiency, increase yield, reduce thermal stress, reduce fluorine contamination, increase an overlay window, and decrease overlay errors.