Backside Gate Contact Layout for Threshold Voltage Control
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in maintaining device performance and reliability due to issues such as threshold voltage changes and the need for additional routing space for backside gate contacts, which can lead to shorting and reduced device yield.
Innovation Solution
The formation of semiconductor devices with CFETs that include alternating dummy nanostructures and semiconductor nanostructures, where the bottommost dummy nanostructure has a greater thickness, allowing for the use of a flowable chemical vapor deposition process to create spacers, followed by annealing and etching to form replacement gates and backside gate contacts that overlap channel regions, optimizing threshold voltage control and reducing the need for additional routing space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but threshold voltage control deteriorates and device reliability decreases
Solution Approach 1:
The patent transitions from planar gate contact to three-dimensional backside gate contact configuration. The gate contact is positioned at the backside of the channel region, extending vertically through the substrate, which adds a vertical dimension to the gate control architecture. This dimensional change enables effective threshold voltage control in scaled devices by providing wraparound gate control from the backside, addressing the reliability issues that arise from continued feature size reduction.
Solution Approach 2:
The patent forms the backside gate contact structure before final device operation, including preliminary formation of the gate contact through the substrate, deposition of gate dielectric and gate electrode layers, and establishment of the gate contact's spatial relationship with the channel region. This preliminary structuring ensures proper threshold voltage control is built into the device architecture from the outset, preventing reliability degradation as devices are scaled.
2Reliability
If additional routing space is provided for backside gate contacts, then threshold voltage control is improved, but device area increases and integration density decreases
Solution Approach 1:
The patent merges the backside gate contact structure with the substrate and surrounding device architecture. The gate contact is integrated into the substrate structure, extending through the substrate thickness, and is positioned to overlap with the channel region in the vertical dimension. This merging eliminates the need for separate lateral routing space, as the gate control is achieved through vertical integration rather than lateral expansion, thereby maintaining high integration density while providing effective threshold voltage control.
Solution Approach 2:
The patent utilizes the vertical dimension by positioning the gate contact at the backside of the substrate and extending it through the substrate thickness to overlap with the channel region. This vertical arrangement replaces what would traditionally require lateral routing space, enabling effective threshold voltage control without increasing the device footprint, thus resolving the contradiction between control quality and area consumption.
3Ease of manufacture
If conventional gate contact formation is used, then manufacturing process is simpler, but threshold voltage control is insufficient in scaled devices
Solution Approach 1:
The patent incorporates backside gate contact formation as a preliminary step in the device fabrication sequence. The gate contact structure is formed through the substrate before subsequent processing steps, including deposition of gate dielectric and gate electrode layers. This preliminary formation integrates the advanced threshold voltage control mechanism into the base manufacturing flow, making the complex structure a foundational element rather than an added complexity, thereby improving ease of manufacture relative to alternative approaches.
Solution Approach 2:
The backside gate contact structure serves multiple functions: it provides threshold voltage control, acts as a gate electrode, and integrates with the substrate structure. This multi-functionality consolidates several requirements into a single structural element, simplifying the overall manufacturing process by eliminating the need for separate components or steps that would otherwise be required to achieve the same functionality in scaled devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes threshold voltage changes, enhances device speed and power delivery, improves device yield and reliability, and ensures consistent spacer width, while maintaining increased channel widths and optimized threshold voltage control.
Implementation Method 1
depositing a dielectric material on sidewalls of the fin structure and in the sidewall recesses of the first ones of the dummy nanostructures using a flowable chemical vapor deposition (FCVD) process
Implementation Method 2
An annealing process may then be performed to cure the dielectric material
Data Source
AI summary
In an embodiment, a method includes forming a multi-layer stack over a semiconductor substrate, patterning the multi-layer stack and the semiconductor substrate to form a fin structure, the fin structure including alternating semiconductor nanostructures and dummy nanostructures, where a bottommost dummy nanostructure of the dummy nanostructures has a first thickness, where first dummy nanostructures of the dummy nanostructures are disposed above the bottommost dummy nanostructure, and each of the first dummy nanostructures has a second thickness that is smaller than the first thickness, forming source/drain recesses in the fin structure, etching sidewalls of the first dummy nanostructures and the bottommost dummy nanostructure in the source/drain recesses to form sidewall recesses, forming inner spacers in the sidewall recesses in the first dummy nanostructures and the bottommost dummy nanostructure, and replacing the first dummy nanostructures and the bottommost dummy nanostructure with a gate structure.