Backside Gate Via Structure for Scaled Semiconductor Gate Control
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing smaller and more complex integrated circuits due to limitations in scaling down processes, particularly in forming small-sized devices with efficient gate structures and vias that maintain performance and reliability.
Innovation Solution
The method involves forming a semiconductor device with a backside gate via under a gate structure, utilizing advanced patterning and etching techniques to create precise gate structures and vias, and integrating epitaxial source/drain structures to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If scaling down processes are used to create smaller devices, then functional density increases, but manufacturing precision and reliability deteriorate
Solution Approach 1:
The patent introduces a backside gate via structure that extends the gate control into the vertical dimension beneath the channel. This dimensional change allows for effective gate control in scaled-down devices by utilizing the depth direction rather than only the planar dimensions, thereby maintaining manufacturing feasibility while achieving smaller device footprints and higher functional density.
Solution Approach 2:
The methodology performs preliminary patterning and etching steps to pre-form the gate via structure before final device assembly. By establishing the backside gate via configuration in advance, the process ensures precise alignment and positioning, which maintains manufacturing precision even as device dimensions are reduced to increase functional density.
2Productivity
If device geometry is reduced to increase functional density, then production efficiency improves, but device performance and reliability worsen
Solution Approach 1:
By extending gate control into the vertical dimension through backside gate vias, the invention maintains effective electric field control over the channel even as planar device dimensions are reduced. This dimensional transition allows for smaller device geometries that increase production efficiency while preserving the electrical characteristics and reliability needed for proper device performance.
Solution Approach 2:
The patent modifies the gate structure parameters by introducing a vertical component (backside gate via) rather than relying solely on planar gate dimensions. This parameter change enables the device to maintain adequate gate control strength at reduced sizes, ensuring reliability is preserved while benefiting from the higher production efficiency associated with smaller geometries.
3Manufacturing precision
If advanced patterning and etching techniques are used to form precise gate structures, then device complexity increases, but manufacturing ease deteriorates
Solution Approach 1:
The fabrication process is divided into distinct segments: preliminary patterning to define via locations, selective etching to form the backside gate vias, and subsequent filling and planarization steps. This segmentation of the complex fabrication process into manageable stages allows for precise gate structure formation while making the overall manufacturing process more controllable and less daunting.
Solution Approach 2:
The methodology performs preliminary patterning and alignment steps to pre-establish the exact locations and dimensions of the backside gate vias before executing the etching and filling operations. This preliminary action ensures that the precise gate structures are formed with the correct geometry and positioning, reducing the need for rework and simplifying subsequent manufacturing steps.
Data Source
AI summary
A device includes a channel layer, a gate structure, a source/drain epitaxial structure, and a gate via. The gate structure is across the channel layer. The gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The source/drain epitaxial structure is adjacent the gate structure and is electrically connected to the channel layer. The gate via is under the gate structure and is in contact with the gate electrode.