Backside Gate Via Doping for SRAM Beta Ratio Control
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Solution Overview
Problem
The challenge in manufacturing high-density SRAM devices is achieving a beta ratio greater than 1 while maintaining small cell sizes, which is crucial for cell stability and read operation performance, as scaling down IC dimensions complicates varying active region dimensions and material compositions of gate structures.
Innovation Solution
The introduction of threshold voltage tuning dopants into the WFM layer of pass-gate transistors during gate via formation, combined with dual-side multilayer interconnect structures, allows for adjusting the threshold voltage of pass-gate transistors and increasing the beta ratio without altering the front-end-of-line process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cell size is reduced to increase manufacturing density, then productivity increases, but the beta ratio becomes difficult to maintain greater than 1
Solution Approach 1:
The patent applies local quality by introducing threshold voltage tuning dopants specifically into the gate electrode layer of pass-gate transistors, creating a localized doping region. This allows the pass-gate transistors to have different electrical characteristics (higher threshold voltage) compared to other transistors in the SRAM cell, enabling beta ratio greater than 1 while maintaining small cell dimensions. The localized modification of gate electrode composition in specific regions resolves the contradiction between small cell size and adequate beta ratio.
2Reliability
If the active region dimensions are varied to adjust transistor characteristics, then the beta ratio can be optimized, but the manufacturing complexity increases
Solution Approach 1:
The patent changes the material composition parameter of the gate electrode layer by introducing threshold voltage tuning dopants (such as carbon, nitrogen, oxygen, or fluorine) into the polysilicon gate electrode. This compositional change modifies the threshold voltage of pass-gate transistors without requiring variations in active region dimensions or complex multi-step doping processes. The parameter change in gate electrode composition provides a simplified manufacturing approach to achieve optimized beta ratio.
3Reliability
If the gate structure material composition is adjusted to change threshold voltage, then transistor performance improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent implements preliminary action by incorporating threshold voltage tuning dopants into the gate electrode layer during the gate formation process itself, before subsequent transistor fabrication steps. The dopants are introduced into the polysilicon gate electrode material in advance, and then the gate electrode is formed as a single integrated structure. This preliminary incorporation of dopants simplifies the manufacturing process compared to post-formation doping methods, as it combines material composition adjustment with the gate formation step in a unified process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances SRAM cell stability by ensuring a beta ratio greater than 1, improving static noise margin and maximum voltage levels during read operations, while maintaining manufacturing efficiency.
Implementation Method 1
The dopant may be introduced into the WFM layer through the gate via opening formed in the dielectric structure
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack across the fin-shaped structure, selectively removing the sacrificial layers to release the channel layers as channel members, depositing a dummy layer in space between the channel members, removing the dummy gate stack, removing the dummy layer, forming a gate structure to wrap around each of the channel members, depositing a backside dielectric layer on a backside of the semiconductor device, patterning the backside dielectric layer to form a backside gate via opening directly under the gate structure, doping a threshold voltage tuning dopant into the gate structure through the backside gate via opening, and after the doping of the threshold voltage tuning dopant, forming a backside gate via in the backside gate via opening.