Self-Aligned Backside Gate Via for Compact Fin Transistors
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Solution Overview
Problem
Existing semiconductor technologies face challenges in achieving compact, high-quality transistors with self-alignment of components and cost-effective manufacturing.
Innovation Solution
A method involving the formation of a semiconductor structure with a sacrificial gate, gate spacers, and a self-aligned via by etching from the frontside of the substrate, allowing precise control of the via's position and alignment, enabling a compact and high-quality transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a compact transistor structure is implemented, then device size is reduced, but manufacturing precision and alignment control become more difficult
Solution Approach 1:
The via is formed to be self-aligned with the gate spacer, eliminating the need for additional alignment steps. The gate spacer itself serves as the alignment reference, and the via automatically positions itself relative to the gate structure through the etching process, ensuring precise alignment in compact transistor structures
Solution Approach 2:
The gate spacer is formed beforehand as a structural element that defines the future via position. By preparing the gate spacer in advance with the correct dimensions and position, the subsequent via formation process automatically achieves the required alignment precision without needing separate alignment operations
2Reliability
If self-alignment of via with gate spacer is achieved, then short circuit risk is reduced, but manufacturing process complexity increases
Solution Approach 1:
The via formation process uses the gate spacer as its own alignment reference, automatically positioning itself correctly relative to the gate structure. This self-aligning mechanism inherently prevents short circuits by ensuring proper spacing between the via and gate, while adding minimal process complexity since it leverages existing structures
Solution Approach 2:
The via is formed by etching from the frontside of the substrate, creating a vertical structure that extends through the substrate thickness. This vertical dimension provides natural alignment with the horizontal gate spacer structure, achieving reliable positioning through geometric constraints rather than complex process control
3Manufacturing precision
If via position is precisely controlled, then transistor quality is improved, but manufacturing cost increases
Solution Approach 1:
The via automatically positions itself relative to the gate spacer through the etching process, using the gate spacer as an inherent alignment reference. This self-aligning approach achieves precise via positioning without requiring expensive additional alignment equipment or multiple lithography steps, maintaining cost-effectiveness
Solution Approach 2:
The gate spacer serves multiple functions: it acts as a structural element defining the gate region, provides electrical isolation, and simultaneously serves as the alignment reference for via formation. This multi-functionality eliminates the need for separate alignment markers or additional process steps, reducing manufacturing complexity and cost
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method ensures high-quality transistors with reduced risk of short circuits and enables efficient, low-cost manufacturing by ensuring precise alignment and self-alignment of components.
Implementation Method 1
forming a first trench between the first and the second gate spacer, by etching, from a frontside of the substrate, the sacrificial gate; forming a hole by etching from the frontside of the substrate, the hole extending from a bottom of the first trench towards a backside of the substrate
Implementation Method 2
depositing metal in the first trench and in the hole such that the metal deposited in the first trench forms at least part of a gate for the at least one channel of the fin
Implementation Method 3
etching the substrate from the backside of the substrate, to expose at least part of the metal in the hole
Data Source
Figure 1a~1b
Figure 2
Figure 3a
AI summary
A method for forming a semiconductor structure (1), the method comprising: forming a fin (20) on top of a substrate (10); forming a sacrificial gate (30) straddling the fin (20); forming first (40) and second (50) gate spacers on opposite sides of the sacrificial gate (30); forming a first trench (60) between the first (40) and second (50) gate spacer, by etching the sacrificial gate (30); forming a hole (80) by etching from the frontside (11) of the substrate (10), the hole (80) extending from a bottom (61) of the first trench (60) towards a backside (12) of the substrate (10), said act of forming the hole (80) being subsequent to said act of etching the sacrificial gate (30); depositing metal in the first trench (60) and in the hole (80); etching the substrate (10), to expose the metal in the hole (80); forming a backside metal track (101) on the exposed metal.