Backside Gate Via Layout for Scaled Semiconductor Gates
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing smaller and more complex integrated circuits due to limitations in scaling down processes, particularly in forming small-sized devices with efficient gate structures and vias that maintain performance and reliability.
Innovation Solution
The method involves forming semiconductor devices with a backside gate via under a gate structure, utilizing advanced patterning and etching techniques to create precise gate structures and vias, and integrating epitaxial source/drain structures to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional scaling down processes are used to create smaller circuits, then geometry size decreases and production efficiency increases, but manufacturing precision and reliability deteriorate due to limitations in forming small-sized devices with efficient gate structures and vias
Solution Approach 1:
The patent inverts the conventional approach by forming the gate structure before the semiconductor fins rather than after. This reversal allows for better control of gate dimensions and positioning, improving manufacturing precision while maintaining the benefits of scaling down for production efficiency
Solution Approach 2:
The gate structure is formed in advance before the fins are created. This preliminary action enables precise definition of gate parameters early in the process, ensuring manufacturing precision is maintained even as geometry scales down for higher productivity
2Ease of manufacture
If conventional gate structure formation methods are used, then manufacturing process is simpler, but device performance and reliability deteriorate due to inability to achieve precise gate control and efficient via structures
Solution Approach 1:
By reversing the sequence to form gates before fins, the patent achieves precise gate control that improves device reliability, while the method remains integrated into the existing fabrication flow to maintain ease of manufacture
Solution Approach 2:
The manufacturing process is segmented into distinct stages with the gate formation as a separate preliminary step. This segmentation allows for optimized control of gate structure parameters, enhancing reliability without significantly complicating the overall manufacturing process
3Productivity
If geometry size is scaled down to increase functional density, then more circuits fit per chip area and production efficiency improves, but manufacturing precision and device performance deteriorate due to challenges in forming small-sized devices with efficient structures
Solution Approach 1:
The inverted sequence of forming gates before fins enables precise control of gate dimensions even at scaled-down geometries, maintaining manufacturing precision while allowing functional density and production efficiency to increase through continued scaling
Data Source
AI summary
A device includes a channel layer, a gate structure, a source/drain epitaxial structure, and a gate via. The gate structure wraps around the channel layer. The gate structure includes a gate dielectric layer and a gate electrode over the gate dielectric layer. The source/drain epitaxial structure is adjacent the gate structure and is electrically connected to the channel layer. The gate via is under the gate structure and is in contact with a bottom surface of the gate electrode.