Backside Gate-Via SRAM Tuning for Beta Ratio Stability
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Solution Overview
Problem
The challenge in manufacturing high-density SRAM devices is achieving a beta ratio greater than 1 while maintaining small cell sizes, which is crucial for cell stability and read operation reliability, as scaling down IC dimensions complicates varying active region dimensions and material compositions of gate structures.
Innovation Solution
The introduction of threshold voltage tuning dopants into the WFM layer of pass-gate transistors during gate via formation, combined with dual-side multilayer interconnect structures, allows for adjusting the threshold voltage of pass-gate transistors and increasing the beta ratio without altering the front-end-of-line process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the cell size is reduced to increase storage density, then the productivity and production efficiency improve, but the beta ratio becomes difficult to maintain greater than 1, compromising SRAM cell stability
Solution Approach 1:
The patent applies local quality by introducing threshold voltage tuning dopants specifically into the gate electrode layer of pass-gate transistors, creating a localized doping region. This allows the pass-gate transistors to have different electrical characteristics (higher threshold voltage) compared to other transistors in the SRAM cell, thereby achieving beta ratio greater than 1 while maintaining small cell dimensions. The localized modification of gate electrode properties enables differential transistor performance without increasing overall cell size.
2Reliability
If the active region dimensions are varied to adjust transistor characteristics, then the beta ratio can be optimized, but the manufacturing complexity increases due to scaling constraints
Solution Approach 1:
The patent employs parameter changes by modifying the threshold voltage of pass-gate transistors through controlled doping of the gate electrode layer. Instead of varying active region dimensions or material compositions during the front-end-of-line process, the invention changes the electrical parameter (threshold voltage) through a subsequent doping step. This approach optimizes the beta ratio by adjusting transistor electrical characteristics rather than physical dimensions, thereby reducing manufacturing complexity associated with precise dimensional control at scaled dimensions.
3Reliability
If the material composition of gate structures is modified to adjust transistor performance, then the beta ratio improves, but the manufacturing process becomes more complex
Solution Approach 1:
The patent applies preliminary action by forming the gate electrode layer with a composition suitable for subsequent doping. The gate electrode is prepared in advance during the front-end-of-line process with materials that can accept threshold voltage tuning dopants. This preliminary preparation enables the later doping step to successfully modify the threshold voltage without requiring complex material deposition or process changes, thereby improving beta ratio while maintaining manufacturing simplicity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances SRAM cell stability by ensuring a beta ratio greater than 1, improving static noise margin and maximum voltage levels during read operations, while maintaining manufacturing efficiency.
Implementation Method 1
The introduction of threshold voltage tuning dopants into the WFM layer of pass-gate transistors during gate via formation
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a stack that includes channel layers interleaved by sacrificial layers, patterning the stack to form a fin-shaped structure, forming a dummy gate stack across the fin-shaped structure, selectively removing the sacrificial layers to release the channel layers as channel members, depositing a dummy layer in space between the channel members, removing the dummy gate stack, removing the dummy layer, forming a gate structure to wrap around each of the channel members, depositing a backside dielectric layer on a backside of the semiconductor device, patterning the backside dielectric layer to form a backside gate via opening directly under the gate structure, doping a threshold voltage tuning dopant into the gate structure through the backside gate via opening, and after the doping of the threshold voltage tuning dopant, forming a backside gate via in the backside gate via opening.