Backside Transistor Contacts Using Germanide Layers for Low Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The resistance of metal interconnects to source/drain regions in integrated circuits (ICs) cannot be effectively reduced on the backside of semiconductor substrates due to the inability to form silicide layers at high temperatures without damaging frontside metallization layers.
Innovation Solution
Incorporating germanide layers in backside contacts to transistors, formed at lower temperatures, to reduce resistance between source/drain regions and metal contacts, while avoiding damage to frontside metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicide layers are formed at high temperatures to reduce contact resistance, then electrical resistance is reduced, but frontside metallization layers are damaged
Solution Approach 1:
The patent changes the temperature parameter from high temperature (700-900°C for silicide) to low temperature (350-450°C for germanide) while maintaining the functional outcome of reducing contact resistance. This parameter change allows the formation of a low-resistance contact without damaging the frontside metallization layers.
Solution Approach 2:
The patent introduces a germanide layer as an intermediary material between the metal contact and the source/drain region. This germanide layer serves as a mediator that provides low contact resistance without requiring the high temperatures that would damage the metallization, thus resolving the contradiction between achieving low resistance and avoiding damage.
2Reliability
If high temperature processes are used to form silicide layers, then low resistance interfaces are achieved, but frontside metallization integrity is compromised
Solution Approach 1:
The patent fundamentally changes the temperature parameter from high (700-900°C) to low (350-450°C), enabling the formation of germanide layers that achieve low interface resistance without compromising the structural integrity and composition stability of the frontside metallization layers.
Solution Approach 2:
The germanide layer acts as a sacrificial or disposable intermediate layer that can be formed at low temperatures. It provides the necessary low-resistance interface function without requiring the high-temperature processes that would threaten the longevity and integrity of the more critical metallization layers.
3Area of stationary object
If backside metallization is added to provide additional routing area, then routing capacity is improved, but contact resistance increases due to inability to form silicide
Solution Approach 1:
The patent changes the formation temperature parameter for backside contacts from high temperature (required for silicide) to low temperature (germanide formation at 350-450°C). This enables the backside metallization to achieve low contact resistance while providing the additional routing area benefit.
Solution Approach 2:
The germanide layer serves as an intermediary that enables low-resistance contacts in the backside metallization. Without this intermediary approach, the backside routing area would be useless due to high contact resistance. The germanide mediator makes the backside metallization functional and useful for additional routing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the electrical resistance of backside metal contacts without subjecting the IC to high temperatures, thereby increasing drive currents and maintaining the integrity of frontside metallization layers.
Implementation Method 1
a germanide layer disposed between the second metal contact and the first source/drain region of the second transistor
Implementation Method 2
formed at lower temperatures, to reduce resistance between source/drain regions and metal contacts, while avoiding damage to frontside metallization layers
Data Source
AI summary
An IC includes a first source/drain region of a first transistor in a semiconductor substrate coupled to a first, frontside metallization layer through a metal contact and a low resistance layer (e.g., silicide layer) formed at a high temperature. A second source/drain region of a second transistor is coupled to a second, backside metallization layer(s) though a backside metal contact and a germanide layer. The germanide layer may be formed between the metal contact and a semiconductor material of the source/drain region at a lower temperature (e.g., 350° C.) than is used in the process to form low resistance (e.g., silicide) layers (e.g., 700° C.). Germanide layers reduce resistance of electrical paths between source/drain regions of transistors and backside metal contacts compared to silicide layers formed at the same lower temperatures and avoid the high temperatures that may cause damage to metallization layers on the integrated circuit (IC).