Backside Heater Structure for OTP Memory Fuse Programming

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Solution Overview

Problem

Existing one-time-programmable (OTP) memory devices face challenges in programming efficiency due to shrinking fuse component dimensions, making it difficult to effectively program the fuses in advanced technology nodes.

Innovation Solution

The OTP memory device incorporates a heater structure on the backside of the substrate, thermally coupled to efuse memory cells on the frontside, which conducts a high current to heat up the fuse components, improving programming efficiency while maintaining compatible dimensions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If fuse component dimensions are shrunk to increase memory density, then memory capacity is improved, but programming efficiency deteriorates

Engineering Contradiction:
Improvememory capacityVSAvoidprogramming efficiency
Core Design Contradiction:
Quantity of substanceVSProductivity

Solution Approach 1:

The heater structure is moved from the frontside to the backside of the substrate, utilizing the third dimension (depth/thickness) to resolve the contradiction. By placing the heater on the backside, the patent achieves thermal coupling with frontside fuse components while maintaining compatible dimensions and avoiding frontside congestion, thereby improving programming efficiency without sacrificing memory capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The substrate itself serves as an intermediary medium for thermal transfer. The backside heater structure conducts heat through the substrate thickness to reach the frontside fuse components, enabling efficient programming of shrunk fuse dimensions while maintaining compact device geometry

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If heater structure is added to improve programming efficiency, then programming yield is improved, but device complexity increases

Engineering Contradiction:
Improveprogramming yieldVSAvoidstructure complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The heater structure is merged with the substrate by forming it on the backside surface, integrating the heating function into the existing device structure rather than adding a separate complex assembly. This approach improves programming yield while minimizing increases in device complexity

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

By utilizing the backside of the substrate (another dimension), the heater structure is positioned without interfering with frontside circuitry, achieving thermal coupling functionality with minimal structural complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The thermal coupling of the backside heater structure enhances the programming yield of efuse memory cells by efficiently heating and altering the state of the fuse components, ensuring reliable and efficient programming.

Implementation Method 1

The plurality of interconnect structures are configured to conduct a substantially high current to elevate a temperature of the fuse component

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Implementation Method 2

the heater structure, electrically isolated from but thermally coupled to the memory cell

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS20250329400A1Semiconductor memory devices with backside heater structure
Publication Date: 2025.10.23 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250329400A1 patent drawing
  • US20250329400A1 patent drawing
  • US20250329400A1 patent drawing

AI summary

A memory device includes a plurality of one-time-programmable (OTP) memory cells formed as a memory array. Each of the plurality of OTP memory cells includes a transistor and a metal structure electrically coupled to each other in series, and the plurality of OTP memory cells are formed on a first side of a substrate. The memory device includes a heater structure, disposed on a second side of the substrate opposite to the first side, that includes a plurality of interconnect structures. The plurality of interconnect structures are configured to conduct a substantially high current so as to elevate a temperature of the resistor when any of the OTP memory cells is being programmed.