Backside Hybrid Bonding for Short Logic-SRAM Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional manufacturing processes struggle to integrate CMOS logic and SRAM memory components on a single die due to incompatible process flows, resulting in lengthy and complex connections that hinder performance and reliability of memory chips like SRAM.
Innovation Solution
A backside-to-backside (B2B) connection interface is introduced, where logic and memory dies are physically and electrically connected through a hybrid bonding method, utilizing conductive paths with tapered contacts and dielectric caps to create a redistribution layer within the B2B interface, reducing connection lengths to less than 1200 nm.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic and memory dies are connected through frontside connections using a large plurality of connections, then electrical connectivity between logic and memory functions is achieved, but connection length and complexity increase, hindering performance and reliability
Solution Approach 1:
The patent inverts the conventional connection approach by connecting logic and memory dies through their backside surfaces rather than frontside surfaces. This inversion allows direct coupling of backside contact pads, dramatically reducing connection length and complexity while achieving reliable electrical connectivity between logic and memory functions
2Ease of manufacture
If conventional manufacturing processes are used to integrate logic and memory on a single die, then manufacturing compatibility is maintained, but process flow incompatibility prevents successful integration
Solution Approach 1:
The patent segments the integration challenge by separating logic and memory fabrication processes. Each die is manufactured independently using its own optimized process flow, then connected through backside bonding. This segmentation allows full manufacturing compatibility while achieving functional integration
Solution Approach 2:
The backside connection interface acts as an intermediary between logic and memory dies. This intermediate bonding layer enables connection between two independently fabricated dies with incompatible process flows, resolving the compatibility issue while maintaining manufacturing flexibility
3Reliability
If logic and memory dies are connected with lengthy connections, then electrical connectivity is established, but connection delays increase, reducing chip performance
Solution Approach 1:
By inverting the connection geometry to use backside surfaces, the patent reduces connection length from millimeters to micrometers. This drastic length reduction minimizes signal propagation delay and resistance, improving both speed and reliability of logic-memory communication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables faster, more reliable memory devices by simplifying internal circuitry and reducing connection delays, improving manufacturing compatibility and chip performance.
Implementation Method 1
A backside-to-backside (B2B) connection interface is introduced, where logic and memory dies are physically and electrically connected through a hybrid bonding method
Data Source
AI summary
A memory device comprises a physically and electrically connected logic die and a memory die. The logic die comprises a logic dielectric layer, with a plurality of logic openings; a logic device layer is disposed on the logic dielectric layer; and a plurality of logic devices, with logic device connections, disposed on/within the logic dielectric layer. The memory die comprises a memory dielectric layer with a plurality of memory openings; a memory device layer is disposed on the memory dielectric layer; and a plurality of memory devices, with memory device connections, disposed on/within the memory device layer. A backside to backside (B2B) connection interface is disposed between the logic dielectric layer and the memory dielectric layer. Connection paths passing through the B2B connection interface enables short back-to-back connections between logic device connections and the memory device connections.