Backside Conductive Structures for IC Routing and Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit design is the difficulty in forming semiconductor devices, particularly in scaling down memory and logic cells, due to limited space, signal and power routing, and electrical isolation issues, which complicates the formation of semiconductor devices in memory or logic cells.
Innovation Solution
The formation of integrated circuits with backside conductive structures that extend through the device layer to contact frontside contacts, using etching processes to expose and connect with frontside source or drain regions and dielectric walls, allowing for efficient signal and power routing between frontside and backside contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional frontside-only contact routing is used, then device layout is simple, but signal and power routing efficiency deteriorates due to limited space
Solution Approach 1:
The patent introduces backside contacts and through-device conductive structures that extend from the frontside through the device layer to the backside, adding a vertical dimension to the routing architecture. This enables signals and power to be routed through the thickness of the device, effectively creating a three-dimensional interconnect system that overcomes the planar space limitations of conventional frontside-only routing.
2Quantity of substance
If device size is reduced to increase density, then integration density improves, but electrical isolation between adjacent devices deteriorates
Solution Approach 1:
The patent employs dielectric walls that extend through the device layer to partition adjacent devices, creating electrical isolation barriers. These segmented dielectric structures physically separate conductive regions of neighboring devices, preventing parasitic coupling and leakage currents while allowing the devices to be closely spaced for high integration density.
Solution Approach 2:
The patent applies different dielectric materials with appropriate properties in specific locations: low-k dielectric materials are used in regions where electrical isolation is critical, while other dielectric materials are used in regions requiring different electrical characteristics. This localized material selection optimizes both isolation performance and device density.
3Productivity
If through-device conductive structures are added for routing, then signal and power routing efficiency improves, but manufacturing complexity increases
Solution Approach 1:
The patent forms conductive regions and dielectric walls in predetermined patterns during the device fabrication process, before final device assembly. Through-device conductive structures are prepared in advance by forming conductive regions that extend through the device layer, and dielectric walls are deposited and patterned to create isolation structures, simplifying subsequent assembly steps.
Data Source
Figure 1A~1B
Figure 1C
Figure 2A~2B
AI summary
Techniques are provided herein to form an integrated circuit that includes one or more backside conductive structures that extend through the device layer to contact one or more frontside contacts, such as frontside source or drain contacts. In an example, a given semiconductor device along a row of such devices may be separated from an adjacent semiconductor device along the row by a gate cut. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure around the semiconductor regions of the devices and also extends between source or drain regions of the devices. A backside conductive structure may extend through portions of the source or drain regions and also through a portion of one of the dielectric walls within the gate trench to contact one or more frontside contacts on the source or drain regions.