Backside IC Routing Structure for More Via Landing Spots
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Solution Overview
Problem
The miniaturization of integrated circuits has led to stricter design and manufacturing specifications, as well as reliability challenges, particularly in terms of routing flexibility and via landing spots.
Innovation Solution
The integrated circuit design includes a first power rail, a second power rail, a first signal line, first and second active regions, and a first conductive line, which are strategically positioned to increase routing flexibility and via landing spots by electrically coupling the active regions to the signal line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the integrated circuit is miniaturized to reduce device size and power consumption, then device size and power consumption are reduced, but routing flexibility and via landing spots are reduced
Solution Approach 1:
The patent introduces a mid-level conductive structure between the active region and the second conductive layer, adding a dimensional layer to the routing architecture. This mid-level structure provides additional via landing spots and routing paths without increasing the planar footprint of the device, thereby maintaining routing flexibility while achieving miniaturization.
Solution Approach 2:
The patent implements a nested routing architecture where the mid-level conductive structure is positioned within the vertical space between the first conductive layer (active region level) and the second conductive layer. This nesting approach allows multiple routing levels to be stacked vertically, increasing routing capacity without expanding the device area.
2Productivity
If the integrated circuit is miniaturized to increase functionality at higher speeds, then functionality and speed are improved, but manufacturing precision and reliability become more difficult to maintain
Solution Approach 1:
The patent divides the conductive routing into multiple separate layers: a first conductive layer at the active region level, a mid-level conductive structure, and a second conductive layer. This segmentation allows each layer to be independently formed and optimized, reducing the cumulative manufacturing complexity and improving precision control for each individual layer while achieving high functionality.
Solution Approach 2:
By adding the mid-level conductive structure as an intermediate layer, the patent creates a three-tier vertical routing architecture. This dimensional approach distributes the routing functionality across multiple levels, reducing the density and manufacturing difficulty on any single layer while maintaining overall high functionality and speed performance.
3Area of moving object
If conventional routing structures are used in miniaturized devices, then device size is reduced, but routing resources and flexibility are insufficient
Solution Approach 1:
The patent vertically stacks three conductive layers (first conductive layer, mid-level conductive structure, and second conductive layer) to create additional routing resources. This vertical dimensionality multiplication increases the quantity of available routing paths and via landing spots without increasing the horizontal device area, effectively providing more routing resources in a miniaturized footprint.
Solution Approach 2:
The mid-level conductive structure is nested within the vertical space between the first and second conductive layers, creating a compact multi-layer routing system. This nesting configuration maximizes the use of vertical space to multiply routing resources while maintaining a small device footprint.
Data Source
AI summary
A method of fabricating an integrated circuit includes fabricating a set of transistors and a dummy via in a front-side of a substrate, performing thinning on a back-side of the substrate opposite from the front-side, fabricating a first set of vias and a first set of conductors on the back-side of a thinned substrate on a first level, the first set of conductors being electrically coupled to the set of transistors by the first set of vias, fabricating a second set of vias on the back-side of the thinned substrate, and depositing a conductive material on the back-side of the thinned substrate on a second level thereby forming a second set of conductors, the second set of conductors being electrically coupled to the first set of conductors by the second set of vias.