Backside Inductor Layout in 3DICs for EMI Isolation
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Solution Overview
Problem
In three-dimensional integrated circuits (3DICs), the positioning of inductors relative to semiconductor devices poses challenges in achieving optimal electrical isolation and minimizing electromagnetic interference (EMI), as inappropriate distances can lead to increased occupation area, inferior electrical properties, and higher production yields, while insufficient isolation results in EMI issues.
Innovation Solution
The inductor is positioned on the backside of a semiconductor wafer, separated from devices by a specific distance, creating no keep-out zone on the front side, which allows for increased routing area and reduced EMI, maintaining similar resistance to other approaches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the inductor is positioned close to the semiconductor device on the front side, then the occupation area is reduced, but the electrical isolation deteriorates and EMI increases
Solution Approach 1:
The inductor is moved from the front side (2D plane) to the backside of the semiconductor wafer, utilizing the third dimension (depth/thickness) to achieve spatial separation. This dimensional transition allows the inductor to be positioned away from sensitive devices while maintaining compact overall footprint, thereby improving electrical isolation without significantly increasing occupation area.
Solution Approach 2:
The semiconductor wafer substrate acts as an intermediary barrier between the inductor and the semiconductor devices. By positioning the inductor on the backside, the wafer thickness and material properties provide natural electromagnetic shielding and electrical isolation, reducing EMI to the devices on the front side.
2Object-affected harmful factors
If the inductor is positioned far from the semiconductor device, then EMI is reduced, but the routing area increases
Solution Approach 1:
By transitioning the inductor position to the backside of the wafer, the routing paths can be optimized independently on both front and back sides. This allows for shorter, more direct interconnects between the inductor and devices through via structures, reducing the overall routing area while maintaining sufficient distance for EMI reduction.
3Area of stationary object
If the inductor is positioned on the front side with devices, then the routing area is maximized, but the electrical isolation deteriorates
Solution Approach 1:
The backside positioning of the inductor utilizes the unused space on the reverse side of the wafer, effectively doubling the available routing area. This allows comprehensive routing without compromising electrical isolation, as the inductor is physically separated from the device layer by the wafer substrate.
Data Source
AI summary
An integrated circuit includes a first semiconductor wafer, a second semiconductor wafer, a first interconnect structure, a first through substrate via, and an under bump metallurgy (UBM) layer. The first semiconductor wafer has a first side of the first semiconductor wafer. The second semiconductor wafer is coupled to the first semiconductor wafer, and is over the first semiconductor wafer. The second semiconductor wafer has a first device in a first side of the second semiconductor wafer. The first interconnect structure is on a second side of the first semiconductor wafer opposite from the first side of the first semiconductor wafer. The first interconnect structure includes an inductor below the first semiconductor wafer. The first through substrate via extends through the first semiconductor wafer. The first through substrate via electrically couples the inductor to at least the first device. The UBM layer is on a surface of the first interconnect structure.