Backside Interconnect Structure for Simpler Semiconductor BEOL Routing
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Solution Overview
Problem
The complexity of manufacturing and integration in semiconductor devices leads to increased fabrication costs and time due to additional process steps, necessitating an improvement in the manufacturing process.
Innovation Solution
A semiconductor device design featuring a backside contact with an interconnect part that includes a lower and upper redistribution layer, an interconnect frame, and a passivation structure, which simplifies the back-end-of-line routing and reduces fabrication costs and time through a modular design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional manufacturing and integration methods are used for semiconductor devices, then device functionality and integration are achieved, but fabrication cost and time increase due to complicated steps and operations
Solution Approach 1:
The semiconductor device is divided into distinct functional modules: a first substrate containing a first device, a second substrate containing a second device, and an interconnect structure connecting them. This segmentation allows each module to be manufactured and tested independently before final integration, reducing overall manufacturing complexity while maintaining high functionality.
Solution Approach 2:
The patent transitions from planar integration to three-dimensional stacking by placing the first device on a first substrate, the second device on a second substrate, and connecting them through vertical interconnect structures. This dimensional change enables higher integration density without increasing lateral process complexity.
2Adaptability or versatility
If traditional manufacturing and integration methods are used for semiconductor devices, then device functionality is achieved, but fabrication time increases due to additional process steps
Solution Approach 1:
The first device and second device are manufactured and prepared on their respective substrates before final assembly. This preliminary fabrication allows parallel processing of multiple devices, reducing total fabrication time compared to sequential assembly methods.
Solution Approach 2:
By segmenting the device into separately manufactured modules that are later integrated, the patent enables concurrent fabrication of multiple components, significantly reducing overall manufacturing cycle time while maintaining full device functionality.
3Adaptability or versatility
If traditional manufacturing and integration methods are used for semiconductor devices, then device functionality is achieved, but fabrication cost increases due to complicated steps and operations
Solution Approach 1:
The patent divides the semiconductor device into separately manufacturable modules (first device on first substrate, second device on second substrate, and interconnect structure). This segmentation enables standardized mass production of each module type, reducing per-unit fabrication costs while preserving complete device functionality.
Solution Approach 2:
By moving to three-dimensional stacking architecture, the patent achieves higher functionality in a compact form factor, reducing the need for complex lateral interconnections and associated manufacturing steps, thereby lowering fabrication costs.
Data Source
AI summary
The present disclosure provides a method for preparing a semiconductor device. The method includes forming a sacrificial source/drain structure over a first carrier substrate; forming a redistribution structure over the sacrificial source/drain structure; attaching the redistribution structure to a second carrier substrate; removing the first carrier substrate after the redistribution structure is attached to the second carrier substrate; replacing the sacrificial source/drain structure with a first source/drain structure; forming a backside contact over and electrically connected to the first source/drain structure; and forming an interconnect part over the backside contact.