Self-Aligned Backside Interconnect Layout for Lower Contact Resistance
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Solution Overview
Problem
As integrated circuit (IC) devices miniaturize, the complexity and parasitic resistance/capacitance of contacts and interconnects increase, leading to manufacturing cost and performance issues due to limited routing area and material scaling challenges.
Innovation Solution
A semiconductor structure with self-aligned backside interconnects is developed, featuring a gate stack, channel structure, source/drain structures, and a backside dielectric and conductive structure, where the backside conductive structure extends along a direction greater than the channel width, formed through a manufacturing process involving epitaxial stop layer removal and sacrificial material handling to reduce contact resistance and increase process margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If IC devices are miniaturized to advance computing power, then component density increases, but routing complexity and parasitic resistance/capacitance increase
Solution Approach 1:
The patent introduces backside interconnects that extend conductive structures from the front surface through the substrate to the back surface, adding a third dimension (depth) to the interconnect architecture. This allows routing paths to utilize the vertical dimension through the substrate, reducing surface routing complexity while maintaining high component density.
Solution Approach 2:
The interconnect structure is segmented into front-side contacts, mid-substrate conductive regions, and back-side interconnects. This segmentation allows different portions of the interconnect to be optimized independently, with each segment serving specific functional requirements while collectively reducing overall routing complexity.
2Length of moving object
If IC devices are miniaturized, then component size decreases, but parasitic resistance and capacitance of contacts and interconnects increase
Solution Approach 1:
By extending conductive structures through the substrate depth dimension, the patent creates three-dimensional interconnect paths. This increases the effective cross-sectional area for current flow without increasing surface footprint, thereby reducing parasitic resistance while maintaining miniaturized component sizes.
Solution Approach 2:
The patent employs multiple conductive materials with different properties in different regions of the interconnect structure. High-conductivity materials are used in critical current paths to minimize parasitic resistance, while other regions use materials optimized for specific electrical or mechanical requirements.
3Area of stationary object
If routing area is reduced due to miniaturization, then device area decreases, but manufacturing cost increases due to increased routing complexity
Solution Approach 1:
The patent forms conductive regions within the substrate before final device assembly, establishing the three-dimensional interconnect framework in advance. This preliminary structuring simplifies subsequent manufacturing steps and enables automated processing, reducing overall manufacturing cost despite the increased interconnect complexity.
Solution Approach 2:
The backside interconnect structure serves multiple functions simultaneously: it provides electrical interconnection, acts as a structural support element, and enables thermal management pathways. This multi-functionality reduces the need for separate dedicated structures, simplifying manufacturing processes.
Data Source
AI summary
Disclosed are techniques for a semiconductor structure. In an aspect, a semiconductor structure includes a gate stack extending along a first direction in a front portion of the semiconductor structure, the gate stack including a first gate structure; a first channel structure disposed through the first gate structure and extending along a second direction; a first source/drain (S/D) structure adjacent the first gate structure and electrically coupled to the first channel structure; a backside dielectric layer disposed in a back portion of the semiconductor structure opposing the front portion; and a backside conductive structure in contact with the first S/D structure and disposed at least partially in the back portion of the semiconductor structure and through the backside dielectric layer. The backside conductive structure has a length in the first direction greater than a width of the first channel structure in the first direction.