Bidirectional Backside Interconnect Layout for Dense IC Routing
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Solution Overview
Problem
The challenge of scaling multi-gate and nanowire transistors is exacerbated by the constraints on lithographic processes, leading to a trade-off between feature pattern dimensions and spacing, which affects power delivery and signal routing, resulting in increased power consumption and layout constraints.
Innovation Solution
Implementing bidirectional backside interconnects with a two-pass litho-etch or litho-etch-metallization scheme, allowing for tight-pitch metal lines in both orthogonal and parallel directions within the same layer, and incorporating contact structures over active gate regions to reduce layout space and power network resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithographic processes are used to pattern transistor features, then manufacturing simplicity is maintained, but the spacing between features must be increased, leading to larger layout area and reduced device density
Solution Approach 1:
The patent introduces bidirectional backside interconnects that extend the interconnection dimension from the front surface to the back surface of the semiconductor device. This allows power and signal routing to occur in three-dimensional space rather than being constrained to two-dimensional planar routing, thereby reducing the layout area required on the front surface while maintaining manufacturing precision through standard lithographic processes.
2Area of stationary object
If feature spacing is reduced to increase device density, then layout area is reduced, but lithographic process constraints are exceeded, affecting manufacturing precision
Solution Approach 1:
By routing interconnects bidirectionally through the backside of the device, the patent enables tighter feature spacing on the front surface without compromising lithographic precision. The additional spatial dimension provided by backside routing relieves the constraint on planar feature spacing, allowing higher device density while maintaining manufacturable feature dimensions.
3Loss of energy
If more interconnect layers are added to improve power delivery, then power network performance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent inverts the conventional unidirectional front-side interconnect approach by implementing bidirectional routing that extends to the back surface. This allows power and signal delivery to occur through the thickness dimension of the device, providing additional routing paths that reduce power network resistance without requiring additional lateral interconnect layers, thereby reducing device complexity and manufacturing cost.
Data Source
Figure 1
Figure 2A(a)~2A(g)
Figure 2B(a)~2B(h)
AI summary
Structures having bidirectional backside interconnects are described. In an example, an integrated circuit structure includes a front side structure including a device layer having a plurality of nanowire-based transistors or a plurality of fin-based transistors, and a plurality of metallization layers above the plurality of nanowire-based transistors or the plurality of fin-based transistor of the device layer. A backside structure is below the plurality of nanowire-based transistors or the plurality of fin-based transistor of the device layer. The backside structure includes a metallization layer having bidirectional backside interconnects, the bidirectional backside interconnects including a first set of conductive lines along a first direction and a second set of conductive lines along a second direction orthogonal to the first direction.